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OMAP-L138: IPC Notify Mechanism

Part Number: OMAP-L138

Hi,

I'm testing out using the IPC library to send messages between the ARM9 and DSP CPU's of the OMAP-L138.

Right now in the example I created one processor uses MessageQ_get() to read a message, and another uses MessageQ_put() to write a message.

Both the ARM9 and DSP CPU's are running TI RTOS and 1 task in each are doing the read/write communication.

I've searched the IPC documentation but could not find out specifically how a task calling MessageQ_get() is woken up when MessageQ_put() is called.

Is there an interrupt that is triggered, or is there a polling mechanism being used, or something else?

I'm just trying to understand better how a task blocking on MessageQ_get() is woken up.

Thanks,

Ben

  • Hi Ben,

    Unfortunately on OMAP-L138, IPC does not support the ARM core running RTOS, only Linux. 

    You can use the CHIPSIG registers to generate interrupts from one core to another.

    Please see the following threads for some discussion around this topic. 

    Regards,
    Sahin

  • Hi Sahin,

    Thanks for the additional resources, I will read up on those.

    The project I made uses TI RTOS in both the ARM9 and DSP CPU's.

    I'm using MessageQ_put() and MessageQ_get().

    Is the message queue not part of the IPC module?

    It's currently working with no issues even though I'm not using Linux on the ARM9.

    Ben

  • Hi Ben,

    Yes MessageQ is part of the IPC module. The RTOS <> RTOS IPC use-case, specifically, is not officially supported, i.e. it was never an official feature released and has not been thoroughly tested on our end. I'm glad to hear it's working on your end however.

    To answer your original question

    Benjamin Michaud said:

    I've searched the IPC documentation but could not find out specifically how a task calling MessageQ_get() is woken up when MessageQ_put() is called.

    Is there an interrupt that is triggered, or is there a polling mechanism being used, or something else?

    IPC uses the chipsig registers to send an interrupt between cores. You can view the implementation under ~\ipc_3_50_04_08\packages\ti\sdo\ipc\family\da830\

    Regards,
    Sahin

  • Thanks Sahin,

    That's what I was wondering about.

    Ben