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TDA4VM: [TDA4VM] Jailhouse inmate-cell GPIO shared

Part Number: TDA4VM

Hi dear TI friends,

As Jailhouse is a hardware isolation hypervisor, can it share gpio pins between root and inmate cells?

I do test like below, but didn't work. Can TI help to check the feasibility of this scheme?

1. in jailhouse-0.10+gitAUTOINC+b3a68ac89d/configs/arm64/k3-j721e-evm-linux-demo.c

		/* main_gpio0 */ {
			.phys_start = 0x00600000,
			.virt_start = 0x00600000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
		},
		/* main_gpio1 */ {
			.phys_start = 0x00601000,
			.virt_start = 0x00601000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
		},

2. in jailhouse-0.10+gitAUTOINC+b3a68ac89d/configs/arm64/dts/inmate-k3-j721e-evm_SmartCarPTA.dts

		main_gpio0: gpio@600000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x00600000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-parent = <&main_gpio_intr>;
			interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
					<105 1 IRQ_TYPE_EDGE_RISING>,
					<105 2 IRQ_TYPE_EDGE_RISING>,
					<105 3 IRQ_TYPE_EDGE_RISING>,
					<105 4 IRQ_TYPE_EDGE_RISING>,
					<105 5 IRQ_TYPE_EDGE_RISING>,
					<105 6 IRQ_TYPE_EDGE_RISING>,
					<105 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <128>;
			ti,davinci-gpio-unbanked = <0>;
			power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&k3_clks 105 0>;
			clock-names = "gpio";
		};

		main_gpio1: gpio@601000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x00601000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-parent = <&main_gpio_intr>;
			interrupts = <106 0 IRQ_TYPE_EDGE_RISING>,
					<106 1 IRQ_TYPE_EDGE_RISING>,
					<106 2 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <36>;
			ti,davinci-gpio-unbanked = <0>;
			power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&k3_clks 106 0>;
			clock-names = "gpio";
		};

3. running the system

root-cell work normal with gpio pin, but i catch some error log from inmate-cell kernel start log.

root@j7-evm:~# dmesg | grep gpio
[    0.983273] davinci_gpio 600000.gpio: IRQ not populated, err = -6
[    1.000112] davinci_gpio 601000.gpio: IRQ not populated, err = -6

BR,
Jingyan

  • Hi Jingyan,

    I am checking internally on this. I will get back in a day or two. In the meantime can you confirm the SDK version?
    Is it SDK 6.02?

    Best Regards,
    Keerthy

  • Hi Keerthy,

    SDK Version : 06.01.00.05

    Linux version : linux-4.19.73+gitAUTOINC+0cabba2b47-g0cabba2b47

    jailhouse version : jailhouse-0.10+gitAUTOINC+b3a68ac89d

    BR,
    Jingyan

  • Hi Keerthy,

    Addtition infomation,

    If i move whole gpio group into inmate-cell, is seams work.

    like close gpio1 node in root-cell, and add gpio1 node in inmate-cell.

    I see the gpio driver, it seams need request irq from main_gpio_intr, is that because the irq can only request one time?

    because err = -6 is ENXIO, means No such device or address.

    BR,
    Jingyan

  • Jingyan Liang said:
    like close gpio1 node in root-cell, and add gpio1 node in inmate-cell.



    That is the right way.

    What is the use case here? I want to understand that better before i can suggest.

    Best Regards,
    Keerthy

  • Hi Keerthy,

    Our custom baord have some gpio control in system, and root-cell and inmate-cell need to control the pin in one group.

    Like root-cell need control gpio0_44, and inmate-cell need control gpio0_45. With this use case, we need gpio1 both root-cell and inmate-cell.

    BR,
    Jingyan

  • Hi JIngyan,

    That should be possible.

    J721E SoC has 3 sets of GPIOs

    • Group one: WKUP_GPIO0 and WKUP_GPIO1
    • Group two: GPIO0, GPIO2, GPIO4, and GPIO6
    • Group three: GPIO1, GPIO3, GPIO5, and GPIO7

    This allows Linux VMs, RTOS (upto 4 SW entities) to drive the pads in GPIO mode without any conflict.

    So GPIO0 can be used by root-cell for vGPIO0_44 & GPIO2 for vGPIO0_45 in the inmate-cell.

    Best Regards,
    Keerthy

  • Hi Keerthy,

    For TDA4VM SoC chip, wakeup domain only have WKUP_GPIO0, main domain only have GPIO0 & GPIO1, other didn't pinned out.

    And how to create the vGPIO group in Jailhouse cell? Becase if i just move gpio group into inmate-cell, the driver will output error log.

    BR,
    Jingyan

  • Hi Jingyan,

    main_gpio2 is already part of ./configs/arm64/dts/inmate-k3-j721e-evm.dts under inmates.

    I am talking w.r.t TDA4VM Board. That has flexible design w.r.t GPIOs. So gpio_keys has been brought out using gpio2 main domain.

    We have added pinmux for gpio2_0 for example:

    sw10_button_pins_default: sw10_button_pins_default {
    pinctrl-single,pins = <
    /* Set muxmode[3:0] = 7, GPIO group[5:4] = 1 */
    J721E_IOPAD(0x0, PIN_INPUT, 23) /* (AC18) EXTINTn.GPIO2_0 */
    >;
    };

    You need to something similar for gpio2_45  via AE27 pin in the inmate cell. Can you try that?

    Best Regards
    Keerthy

  • Hi Keerthy,

    Thanks, it means,

    GPIO0 has the virtual gpio group GPIO0,2,4,6

    GPIO1 has the virtual gpio group GPIO1,3,5,7

    i will try it first.

    BR,
    Jingyan

  • Hi Jingyan,

    sw10_button_pins_default: sw10_button_pins_default {
    pinctrl-single,pins = <
    /* Set muxmode[3:0] = 7, GPIO group[5:4] = 1 */
    J721E_IOPAD(0xB8, PIN_INPUT, 23) /* (AE27) EXTINTn.GPIO2_0 */
    >;
    };

    Notice the mux mode set tp 23 aka 0x10111

    So the bit4:5 are set to 0x1 telling that we choose combination 1 i.e main_gpio2 & main_gpio3.

    So there is no real need to migrate the main_gpio0/1 to inmate. Inmate already has main_gpio2/3.

    So gpio2_45 should be something like:

    &main_pmx0 {
    mygpio1_pins_default: mygpio1_pins_default {
    pinctrl-single,pins = <
    /* Set muxmode[3:0] = 7, GPIO group[5:4] = 1 */
    J721E_IOPAD(0xb8, PIN_INPUT, 23) /* (AE27) PRG0_PRU0_GPO2.GPIO2_45 */
    >;
    };

    };