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DSP Timers Synchronization

Hello All

There is a simply way to synchronize TIMER0 and TIMER1 with a precision offset.

I am using the  TMS320C6413-500 DSP and Imagine the situation that I have 2 pulse timers, each one with 2us period, but I want the TIMER1 to trigger 600ns after TIMER0

I did not found any direct solution, but perhaps there is some workaround?

best regards

Nuno Pereira




  • Nuno Pereira,

    This is an interesting issue. There is no direct method that I can see for synchronizing two timers precisely. They must be started by writing to their CTL registers and the two writes can cross a divider boundary.

    I can imagine two scenarios for you to consider. Perhaps these ideas will not work for you, but they may suggest to you another creative method to use. It has been a while since I used the C64x timers, so the details below are based on a quick read of the User's Guide; some details may be wrong, but the ideas could work for you.

    1. The easiest scenario to get this precise timing would be to use a single timer to generate the pulses. Your external logic would have to distinguish between the first and the second pulse.

    1a. Set the PRD to the delay required for the first pulse. When the timer reaches that point, generate the first pulse and cause a DSP interrupt. In the ISR, change the PRD to the value for 600ns. The second pulse will be generated at the correct time.

    1b. If it is unreliable to get the ISR to change PRD quickly enough because of system issues and interrupt latencies, you could set the PRD value for 600ns and set the CNT value to something other than 0 to start the first counter delay. For example, if the first counter delay should be 2000ns you could set the PRD to 600ns and the CNT to -1400ns; CNT will overflow above FFFF-to-0000 and then count to 600ns before generating the pulse.

    2. Another scenario is to calibrate the process of starting the two timers. There are many conditions that could affect the precise timing delay between the write to TMR0_CTL and TMR1_CTL (or whatever they are supposed to be named), for example a write FIFO may be in the path so that the actual writes have more time between them than the write instructions that the DSP executes. But as long as the internal clock dividers are the same or deterministicly similar, a workable process can be determined.

    This would likely have to be written in assembly to make sure the instructions do not vary from one build to another, such as due to different compiler versions or compiler switch settings. You could start with C and then look at the assembly output as a place to start. C6000 assembly is very difficult to learn, and you may have problems with this for that reason.

    Read TMR0_CTL
    Write TMR0_CTL
    Delay N cycles (NOPs or something)
    Read TMR1_CTL
    Write TMR1_CTL

    The "Delay N cycles" part can be adjusted so the two timers are precisely in-phase. They will have to be started on different cycles of the divide-by-8 timer clock. The idea is to adjust N so that both timers are started at the exact same phase of that divide-by-8 timer clock.

    This will require you to run this many times looking at the variation of the two pulses. Interrupts will have to be disabled during the five steps to make sure nothing else would impact the timing.

    Scenario 2 may not work or may be too difficult. But I wanted to offer the idea. My apologies if it is not described clearly.



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  • Hello RandyP

    Thanks for your comments.

    After trying initialy option 2, with more and less good results, because I made the function "my_delay" in C, I decide to go to option 1b.

    The results are more and less the same and the complexity it is much lower.

    I believe that could be the perfect solution is there was a way to start several timers by writing in a common register, because all the other solutions will have always instruction execution timming issues.

    best regards

    Nuno Pereira