Hello,
A lot of these questions come from the threads here:
But I think these questions are separate, and probably a little easier to answer
1) Does the AUXCLK pin (on the McASP TX/RX Clock Generator Block Diagram) come from the audio oscillator on the K2G, similar to the AIC codec on the EVMK2G board?
a) If so, does that mean that since the EVMK2G board has the 22.5792 MHz crystal, I'm only capable of 22.050kHz, 44.1kHz, 82.2kHz, etc, sample rates on the audio daughtercard as well?
b) If that is true, can you provide a link or instructions for switching out the crystal? I'm not a hardware guy, personally, but I can forward it to the hardware guys on my team.
2) In a previous thread, it was pointed out that to calculate the sample rate from the bit sample clock, it's "each audio data sample(I2S format) has 2 channels and each channel is 16 bits in our configuration. So to send a data sample(2 channels) you will need 44.1*2*16 = 1411.2 Khz bit clock.", for the example of 44.1kHz audio.
Is the number of "audio data sample" channels the same regardless of how many serializers you use?
3) Given the 22.5792MHz crystal oscillator we have now, I'm trying to achieve 88.2kHz audio (I would like 96kHz after switching crystals, but the clock divider settings should remain the same).
Here are the settings I have for the Mcasp_HwSetupData structs in mcasp_cfg.c:
/* McASP HW setup for receive */ Mcasp_HwSetupData mcaspRcvSetup = { /* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */ /* .rfmt = */ 0x000180F2, /* * 0 bit delay from framesync * MSB first * No extra bit padding * Padding bit (ignore) * slot Size is 32 * Reads from DMA port * NO rotation */ /* .afsrctl = */ 0X00000112, /* I2S mode - 2 slot TDM * Frame sync is one word * Internally generated frame sync * Rising edge is start of frame */ /* .rtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */ /* .rintctl = */ 0x00000000, /* sync error and overrun error */ /* .rstat = */ 0x000001FF, /* reset any existing status bits */ /* .revtctl = */ 0x00000000, /* DMA request is enabled */ { /* .aclkrctl = */ 0x000000A7, /* .ahclkrctl = */ 0x0000C000, /* .rclkchk = */ 0x00000000 } }; /* McASP HW setup for transmit */ Mcasp_HwSetupData mcaspXmtSetup = { /* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */ /* .xfmt = */ 0x000180F6, /* * 0 bit delay from framesync * MSB first * No extra bit padding * Padding bit (ignore) * slot Size is 32 * Reads from DMA port * NO rotation */ /* .afsxctl = */ 0x00000112, /* I2S mode - 2 slot TDM * Frame sync is one word * Rising edge is start of frame * Internally generated frame sync */ /* .xtdm = */ 0x00000003, /* slot 1 and 2 are active (I2S) */ /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */ /* .xstat = */ 0x000001FF, /* reset any existing status bits */ /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */ { /* .aclkxctl = */ 0X000000A7, /* .ahclkxctl = */ 0x0000C000, /* .xclkchk = */ 0x00000000 }, };
The relevant parts being aclkrctl, ahclkrctl, and aclkxctl, ahclkxctl.
The settings indicate the the HF clock divider, and regular clock divider are set to 1 and 8, respectively. Which would give us a final transmit clock rate of 2822400Hz (22.5792MHz / 8).
This means the audio sample rate is 2822400 / 2(channels) / 16(bits per channel) = 88.2kHz, correct? (I just wanted to make sure on this point).
4) If I wanted to set my sample rate higher, I would have to then modify the regular (non HF) clock divider to have smaller divisor. For instance, if I wanted 176.4kHz audio rate, I would need to change the clock divider to 4, as in
/* .aclkxctl = */ 0X000000A3, // should be divisor of 4.
However, when I try that, I get no audio whatsoever. If I try to set the clock divider to 0xAF (divisor of 16), I get what sounds like white noise at the output. What am I doing wrong?