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AM4372: TPS65216 unstable power rails

Part Number: AM4372
Other Parts Discussed in Thread: TPS65216

Dear Champs,

My customer is bring-up AM4372 in their custom board and it was powered by PMIC(TPS65216). They found every power rails of TPS65216 were very unstable during several dozens of seconds and then to be stable.

After the power outputs of TPS65216 were stable, there is no issue to connect JTAG and they are assuming AM4372 can be boot.

These unstable power output of TPS65216 were not observed when one of 1.1V VDD_CORE or 1.8V or 3.3V power rail was not connected, and it would be very helpful if you can guide me where should be checked to resolve this issue.

The each power rail was showed as below during initial dozens of second.

1) LDO1, 0~1.8V, with 565ms period

2) DCDC1, 0~1.1V, with 565ms period

3) DCDC2, 0~1.1V, with 565ms period

4) DCDC3, 0~1.35V, with 565ms period

5) DCDC4, 2.6~3.3V, with 565ms period

    

Thanks and Best Regards,

SI.

  • Hi,

    Please check that you are correctly following www.ti.com/.../spruip2.pdf

  • Sorry. I clicked 'resolve issue' by mistake, and this is not resolved yet.

    Of course, I have checked the documents you mentioned, but I could not find any strange thing.

    I think the only strange thing  IThey are not using RTC and removed RTC related in their HW by referring below.

    I have discussed with  before in below e2e.

    https://e2e.ti.com/support/processors/f/791/t/878210?tisearch=e2e-quicksearch&keymatch=AM4372%20AND%20pmic%20AND%20power

    Do you have any idea what should be checked further?

    Thanks and Best Regards,

    SI. 

  • This seems like the PMIC is resetting for some reason. I am transferring this to the PMIC team for comments.

  • SI,

    Just to be clear, this is not an indication of instability. The rails are stable, and they settle to the correct values, but for some reason the PMIC shuts down and goes into a fault recovery condition.

    If you refer to Figure 5-24. Modes of Operation Diagram on page 38 of the TPS65216 datasheet, you can see that the PMIC starts in the "NO POWER" state, then power is applied and it goes to the "OFF" state, then it goes to "WAIT_PWR_EN". In the "WAIT_PWR_EN" state, all the DCDCs (DCDC1-4) and LDO1 turn on. The sequence takes approximately 38ms (2ms*9 DLYx + 20ms PGOOD delay). After they turn on and the RTC_PWR_EN signal is high (tDG = 10ms deglitch time), the PMIC device enters the "ACTIVE" state. In your scope shots, it is clear that DCDC2 turns on and settles at 1.1V, and this is the last rail to turn on in the sequence. The problem is DCDC2 and the other rails shutdown shortly after they all turn on.

    A fault has occurred (most likely a PGOOD fault because 1 of the 5 regulators is violating the VPG or VOV condition) and the PMIC jumps to the right side of the state machine diagram.

    From ACTIVE ("ANY STATE"), the PMIC starts the power-down sequence, which will last for approximately 500ms. This transitional state is named "SEQ DOWN (500 ms)". Because this is not an Over-Temp fault (OTS), then the PMIC goes through the "RECOVERY" state and back to "WAIT_PWR_EN", then "ACTIVE" and the fault happens again. 

    As a result, it is expected that this cycle will continue, approximately every 548 ms (plus any other delays I have not accounted for), so 565 ms makes perfect sense. This is the expected operation of the PMIC and does not mean it is unstable.

    The issue seems to be related to LDO1. For example, during the time when the PMIC turns off all rails, LDO1 = 1.0-1.1V, and when LDO1 is turned on it appears LDO1 = 1.9-2.0V, which is higher than the allowable VOV=1.05*1.8V=1.89V for >50us (because STRICT=1b by default).

    How did you connect VDDS_RTCCAP_VDD_RTC in your system? VDDS_RTC should be powered by LDO1 (1.8V) which is shown in Table 3 of the Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 User's Guide, and the AM437x should generate CAP_VDD_RTC through an internal LDO (voltage at this pin should measure 1.0V) which is shown Figure 5 in the User's Guide.

    Whatever is causing LDO1 to be >1.89V is the root cause of your problem. I do not know if the RTC domain of AM437x will cause this due to improper connection, or if there is another voltage rail in the system generating 2.5V or 3.3V that we do not know about because we do not have a schematic, but I do know the the PMIC will not generate >1.8V on its own. The PMIC does not randomly increase the voltage on any rail and this is almost always caused by a leakage path through the processor, which comes from another voltage supply that turns on at the wrong time before or during the power-up sequence of the PMIC.

  • Hi Brian and Biser,

    They found some leakage(-1.5A) in the 3.3V power rail as below picture.

    Do you think this leakage in the 3.3V can cause this issue?

    Could you please let me know how this leakage can be removed?

    There is only QSPI flash and DDR3 memory in the board as this is CPU SOM board, and IO board was not attached now.

    Is it possible to send HW schematic to you via mail and check it?

    For VDDS_RTC & CAP_VDD_RTC,

    VDDS_RTC is connected to LDO1(1.8V) and CAP_VDD_RTC is connected to  DCDC1(VDD_CORE) as they are not using internal RTC.

    RTC_KALDO_ENn is connected to VDDS_RTC to disable RTC_LDO.

    We observed power rails after CAP_VDD_RTC opened just for test, but there was no improvement. 

    Thanks and Best Regards,

    SI.

  • I attached HW schematic related with PMIC in below.

    Thanks and Best Regards,

    SI.

  • SI,

    Please provide scope shot of LDO1 zoomed in, showing approximately 10ms from the time LDO1 turns on to the time LDO1 turns off.

    We need to see clearly if VLDO1 > 1.89V for >50us.

    The scope shot you have provided is not clear to me because it does not have any labels. What is Channel 2? DCDC4 is 3.3V, but C2 shows an offset of -5.9V so this cannot be showing a 3.3V supply. 

    Also, this pulse is <5us and I am looking for VOV or VPG for >50us. A 5us glitch or pulse would be filtered out as an acceptable transient condition.

  • HI Brian,

    I am Philip.

    Whether to enable or disable RTC, should we follow Figure 5 schematic as below?

    The customer's schematic did not follow figure 5.

    RTC_PWRONRSTn is connected on GND.

  • Hi Brian,

    In the previous scope shot of 3.3V, “1CH:3.3V(DCDC4), 2CH(PGOOD)".

     

    For 1.8V LDO of TPS65216,

    they found there were overshoot of 1.93V in the 1.8V LDO as below, and it seems state recycle in PMIC was occurred after this overshoot in the 1.8V LDO.

    one strange thing is there was 2.5V in the DCD4(3.3V rail) followed by 1.8V LDO.

    Please check below scope shot and let me know what is the next step.

    -       1CH : LDO1, 2CH : DCDC3, 3CH : DCDC4

    Thanks and Best Regards,

    SI.

  • SI & ,

    Yes, I think the customer should follow Figure 5 in Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 User's Guide, but I do not think this is the root cause of your problem. The AM437x team would need to comment on what might happen if you do not follow Figure 5 wiring. Can you start a new e2e Question to get this answer separately?

    The root cause of your problem appears to be: CPU_STATUS_LED, an AM437x GPIO, is tied to VCC_5V supply through an LED.

    Proposed Solution: Remove resistor R154 and try to power-on system.

    While reviewing your new scope shot, I determined the issue starts as soon as the PMIC tries to start the power-up sequence, but the PMIC only sees the problem when LDO1>2.9V

    Look at LDO1 (Ch1) and DCDC4 (Ch3) in the beginning of the sequence, before LDO1 turns on.

    Both LDO1 and DCDC4 are expected to be 0V at this time, but they are not. So I looked for another source of power before PMIC power-up sequence starts, and that is when I noticed CPU_STATUS_LED, an AM437x GPIO, is tied to VCC_5V. This creates is an obvious leakage through the AM437x GPIO (not fail-safe I/Os), which presents itself as a voltage on LDO1 and DCDC4. The entire power-up sequence is not valid, and when LDO1 does turn on it stops at 1.8V then continues to increase to >1.89V

    When the PMIC recognizes LDO1>1.89V, it shuts itself down but the issue is still present (CPU_STATUS_LED is tied to VCC_5V) so LDO1 and DCDC4 settle to  LDO1=0.9V and DCDC4=2.8V until the PMIC tries to turn on again, and the problem repeats itself.

  • Hi Brian,

    Thanks for your immediate response.

    Unfortunately it was not helped to resolve issue and same issue was occurred even after removing ‘R154’.

     

    Then, do you think what our next step is to check AM4372 HW schematic to find out any other thing to generate leakage in AM4372?

    Thanks and Best Regards,

    SI.

  • Hi Brian,

    Philip found the root cause and the issue was caused by 3.3V connected to oscillator, but 1.8V should be used for oscillator connected to AM4372.

    After disconnecting 3.3V on oscillator, the issue was resolved and PMIC was not restarted.

    But, they still found 3V ramp-up in DCDC4 before 1.8V LDO started as below. Do you think if this is normal or we need to check if there is still a leakage?

    Could you please check below?

    -       1CH : LDO1, 2CH : DCDC3, 3CH : DCDC4

    Thanks and Best Regards,

    SI.

  • SI,

    Good, I am glad to hear Philip found true root cause of VLDO>1.89V which causes PMIC shutdown and prevents processor boot.

    Sung-IL said:
    But, they still found 3V ramp-up in DCDC4 before 1.8V LDO started as below. Do you think if this is normal or we need to check if there is still a leakage?

    No, I do not think this is normal. Although removing R154 did not solve LDO1 issue, I still think CPU_STATUS_LED connected to VCC_5V supply through a Green LED is the most likely root cause of DCDC4=2.8-2.9V before this DCDC converter is enabled.

    If you apply both workarounds at same time:

    • Connect 1.8V from LDO1 to oscillator (OSC1/2) for AM4372. (instead of +3.3V)
    • Remove R154 to disconnect VCC_5V from LED D1 and CPU_STATUS_LED GPIO pin

    what is the result?

    The only thing that can cause DCDC4=2.8-2.9V before PMIC power-up sequence start is a supply voltage >3.0V that is always enabled. Here are the only possible sources I can find in the schematic:

    1. VCC_5V connected through LED D1 to CPU_STATUS_LED GPIO pin of AM4372
    2. USB0_VBUS/USB1_VBUS: connected to pins U23/T25 of AM4372 from connector CN1 pin 114 and CN3 pin 101
    3. VCC_BAT_3V: pins 110,112 do not appear to connect anywhere else on schematic
    4. Any I/O pin on connectors CN1, CN2, or CN3 that connect to AM4372 and are high before VCC_5V is applied to PMIC

    Of all the possible sources on this list, I identified item #1 as the highest risk for causing the issue.