DRA756: uboot no clock output for PHY-less connection

user6232558

Part Number: DRA756

Hi there,

We have a DRA7 customed board, design of which refers EVMX777G-01-40-00 (the evm board). However, there is no output clock in EMAC[0].TXC, when booting to uboot.

# HwEnv

- DRA7 is connected to Marvell Switch 88EA6321 port 2. Switch chip is controlled by a MCU running bare-metal code without IP stack

- This local network is not connect to external network. For controlling switch, only port forwarding is achieved between port 5 and port 6.

- Due to network issue in DRA7 side, port forwarding function is still being verified between port 2 and port 5.

- MCU powers on at frist and configure switch. Then MCU powers on DRA7

# SwEnv

- ubuntu 14

- ti-processor-sdk-linux-automotive-dra7xx-evm-5_00_00_01

# Porting process

- change mux_data.h file with TI pinmux tool generation

- bypass eeprom board detection in board_detection and manually set board_name as dra74x_evm

- change dts

# Verified part

- work normally : serial port, GPIO, LED, emmc, power, CAN

- under varied emac0 speed, emac registers seem not configured

- Under different emac speed 10 100 1000Mbps, {0x48484D84, 0x48485288, 0x4A002554} are identical and equal to {0x00000000, 0x00000000, 0x00003302}

- uboot dts is below

# Problem locating

- Compared with the evm board, after executing uboot/driver/net/cpsw.c -> cpsw_gmii_sel_dra7xx -> writel(reg, priv->data.gmii_sel), EMAC[0]_TXC is able to output clock. But for out customed board, there is no clock at all when running over the same location.

Hope someone able to share insights. Thanks very much !

Best Regards,

Daniel

over 3 years ago

0 Vishal Mahaveer over 3 years ago

TI__Mastermind 32830 points

Hi Daniel,

Can you confirm the mux settings for RGMII0 pins are taking effect?
You can read the padconf registers to confirm (CTRL_CORE_PAD_RGMII0_*)

Regards,
Vishal

0 user6232558 over 3 years ago in reply to Vishal Mahaveer

Intellectual 435 points

Hi Vishal,

Thanks for your reply. I've already posted the result. Some progress I hope to sync with you.

I manually set these padconf again, and there is output clock. My doubts about this are below :

1 why uboot not configure pad

2 where uboot configure these pad

Best Regards,

Daniel

0 Vishal Mahaveer over 3 years ago in reply to user6232558

TI__Mastermind 32830 points

Hi Daniel,

Pad configurations happens in recalibrate_iodelay() API (File: board/ti/dra7xx/evm.c)
https://git.ti.com/gitweb?p=ti-u-boot/ti-u-boot.git;a=blob;f=board/ti/dra7xx/evm.c;hb=refs/heads/ti-u-boot-2018.01#l903

Based on the device detected, padconf table is chosen (defined in board/ti/dra7xx/mux_data.h) and passed to do_set_mux32() API
https://git.ti.com/gitweb?p=ti-u-boot/ti-u-boot.git;a=blob;f=board/ti/dra7xx/evm.c;hb=refs/heads/ti-u-boot-2018.01#l977

Same logic is applied for iodelay table.

Regards.
Vishal

0 user6232558 over 3 years ago in reply to Vishal Mahaveer

Intellectual 435 points

Hi Vishal,

Thanks for your help.

I found do_set_mux_32 is not executed. It enters err branch. In what case, will this happen ?

	/* Setup I/O isolation */
	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Do the muxing here */
	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);

---Progress---

locate here

int __recalibrate_iodelay_start(void)
{
	int ret = 0;

	/* IO recalibration should be done only from SRAM */
	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
		// while(1); not here
		return -1;
	}

	/* unlock IODELAY CONFIG registers */
	writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
	       CFG_REG_8_OFFSET);

	ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
	if (ret)
	{
		while(1); // <-- Stuck here
		goto err;
	}
       */
	ret = isolate_io(ISOLATE_IO);
	if (ret)
		goto err;

	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);

err:
	return ret;
}

Hope for your reply and thanks a lot !

---Solution here---

Edit evm.c and comment goto err Setup I/O isolation part.

Best Regards,

Daniel

0 Vishal Mahaveer over 3 years ago in reply to user6232558

TI__Mastermind 32830 points

Hi Daniel,

Are you accessing any peripheral during this process?

Regards,
Vishal

0 user6232558 over 3 years ago in reply to Vishal Mahaveer

Intellectual 435 points

Hi Vishal,

I may not get your point. I guess what you may want to say :

1 why other peripheral can work normally before changing ?

- Other peripherals can work may finish pad configure with pin-ctrl from dts file

2 After changing, is any peripheral working okay ?

- I think it works okay. Because the customed board can boot to linux and login.

Thanks for your supports for working on clocking problem together. Some suggestion for your woking on TI E2E I would like to put here :

1 Read posted question carefully, and it should be better avoiding ask the thing that the post already contains

2 Try to put what you want to check at a time, instead of do checking operation repeatedly and separately. Save time for both of us

3 Be more professional and try to express idea more clearly and specificly

4 Give answer directly instead of switching to another topic

Thanks so much agian and keep good.

Best Regards,

Daniel

0 Vishal Mahaveer over 3 years ago in reply to Vishal Mahaveer

TI__Mastermind 32830 points

Hi Daniel,

I was trying to ask if any peripheral is being used when bootloader is executing recalibrate_iodelay API.
We have not seen this API fail before. Only reason we could think of is if any peripheral is being used when MLO is doing iodelay recalibration.

You clicked on "This resolved my issue", is the issue resolved?

Regards,
Vishal

0 user6232558 over 3 years ago in reply to Vishal Mahaveer

Intellectual 435 points

Hi Vishal,

I got your point. During booting process, only UART is connected to my PC. I cannot think of any other peripheral is being used. This is another problem and I will open another thread for this.

The issue is resolved when goto err code is commented. I know this fixing may cause other potential problems, but I can focus on DRA7 mac to switch verification again with this resolvement.

Thanks for your confirmation and supports !

Best Regards,

Daniel

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DRA756: uboot no clock output for PHY-less connection