TMS320C6670: About the function CSL_XMC_invalidatePrefetchBuffer()

elijah lee

Part Number: TMS320C6670
Other Parts Discussed in Thread: OMAPL138

Hi, recently I am programming on 6670 plaform, In my application, L1d cache size is 32KB and L2 cache 0KB, some data produced by a coprocessor and stored on the MCSM should be read and processed by the CPU core, so I write the following code:

Line0: ------blank

Line1: CACHE_invL1d(MCSM_Data_Addr, MCSM_Data_Len, CACHE_WAIT**);

Line2: processing the data located in the MCSM_Data_Addr.

But occasionally, the read data of Line2 is not equal to that located in MCSM_Data_Addr.

In order to solve the problem, I modify the code, i.e. adding invalidatePrefetchBuffer operation before CACHE_invL1d,

Line0: CSL_XMC_invalidatePrefetchBuffer();

Line1: CACHE_invL1d(MCSM_Data_Addr, MCSM_Data_Len, CACHE_WAIT**);

Line2: processing the data located in the MCSM_Data_Addr.

But I do not known why CSL_XMC_invalidatePrefetchBuffer() statement should be used. Should CSL_XMC_invalidatePrefetchBuffer() be used before every CACHE_invL1d() statement ? If yes or not, why ?

Thanks for your kind help! Best wishes!

over 3 years ago

0 lding over 3 years ago

TI__Guru* 95265 points

Hi,

C6670 is the same as C6678 for the DSP corepac. If you look at the TI CSL code: pdk_667x_2_0_16\packages\ti\csl\csl_cacheAux.h

static inline void CACHE_invL1d
(
const void* blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
); /*for misra warnings*/
static inline void CACHE_invL1d
(
const void* blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
)
{
uint32_t gie, advisory6;

if ( (wait == CACHE_WAIT ) ||
(wait == CACHE_FENCE_WAIT) )
{
advisory6 = (uint32_t)1U;
}
else
{
advisory6 = 0;
}

if ( advisory6 )
{
/* disable the interrupts */
gie = _disable_interrupts ();
#if !(defined (SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_TPR12))
CSL_XMC_invalidatePrefetchBuffer();
#endif
}

/* Setup the block address and length */
hCache->L1DIBAR = CSL_FMK(CGEM_L1DIBAR_ADDR, (Uint32)blockPtr);
hCache->L1DIWC = CSL_FMK(CGEM_L1DIWC_WC, (Uint32)((byteCnt+((uint32_t)3U))>>2));

/* Determine if we need to wait for the operation to complete. */
if ( (wait == CACHE_WAIT) ||
(wait == CACHE_ONLY_WAIT) )
{
CACHE_invL1dWait();
}
else
{
#if !(defined (SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_TPR12))
if ( (wait == CACHE_FENCE_WAIT) ||
(wait == CACHE_FENCE_ONLY_WAIT ) )
{
(void)_mfence();
/* Add another mfence to address single mfence issue
* Under very particular circumstances, MFENCE may allow
* the transaction after the MFENCE to proceed before
* the preceding STORE completes */
(void)_mfence();
}
#endif
}

if (advisory6)
{
CACHE_AsmNop();
(void)_restore_interrupts (gie);
}
}

CSL_XMC_invalidatePrefetchBuffer() is already part of the cache invalidate function. Also see discussion in: https://e2e.ti.com/support/processors/f/791/p/253690/920869

Regards, Eric

0 elijah lee over 3 years ago in reply to lding

Prodigy 90 points

Thank you very much!

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TMS320C6670: About the function CSL_XMC_invalidatePrefetchBuffer()