Other Parts Discussed in Thread: AM5729, AM5728
Tool/software: TI C/C++ Compiler
Hi All,
Using ti-cgt-c6000_8.3.6 on AM5729/C66x I looked into the generated asm listing of a simple 64-bit integer variable access and found that the loading/storing of the 64bit value is done using two LDW instructions instead of a single LDDW.
For example the following C code:
#include <xdc/std.h>
typedef unsigned long long u64;
u64 testVariable = 0;
u64 GetVar()
{
return testVariable;
}
void SetVar(u64 val)
{
testVariable = val;
}
Compiles into:
29 .global testVariable
30 00000000 .sect ".neardata", RW
31 .align 8
32 .elfsym testVariable,SYM_SIZE(8)
33 00000000 testVariable:
34 00000000 00000000 .bits 0,64
49 00000000 SetVar:
50 ;** --------------------------------------------------------------------------*
51 00000000 008c6362 RETNOP B3,3 ; [] |15|
52 00000004 0200007c! STW .D2T1 A4,*+DP(testVariable) ; [B_D64P] |14|
53 00000008 0280047c! STW .D2T1 A5,*+DP(testVariable+4) ; [B_D64P] |14|
54 ; BRANCH OCCURS {B3} ; [] |15|
66 0000000c GetVar:
69 0000000c 000c0363 RET .S2 B3 ; [B_Sb66] |10|
70 00000010 0200006c! || LDW .D2T1 *+DP(testVariable),A4 ; [B_D64P] |9|
71
72 00000014 0280046c! LDW .D2T1 *+DP(testVariable+4),A5 ; [B_D64P] |9|
73 00000018 00006000 NOP 4 ; [A_L66]
74 ; BRANCH OCCURS {B3} ; [] |10|
Here're my command line settings:
"/home/istvan/ti/ccs1000/ccs/tools/compiler/ti-cgt-c6000_8.3.6/bin/cl6x" -mv6600 -O3 --opt_for_speed=2 -ms0 --define=am5728 --define=core2 --define=SOC_AM572x --define=core2 --symdebug:none --c99 --c++14 --diag_suppress=2170 --diag_warning=225 --diag_wrap=off --display_error_number --auto_inline=0 --analyze_only -k --asm_listing --asm_cross_reference_listing --preproc_with_compile --preproc_dependency="test64.d_raw" --cmd_file="configPkg/compiler.opt" "../test64.c"
I'm wondering why the compilier is not using LDDW/STDW here?
Istvan