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Compiler/STARTERWARE-SITARA: How to read the auxiliary system registers in Sitara uP using TI's StarterWare Code?

Part Number: STARTERWARE-SITARA
Other Parts Discussed in Thread: AM3358

Tool/software: TI C/C++ Compiler

I am nowhere after four months' struggle. Million thanks in advance who helps me out here.

My goal is to R/W to auxiliary system registers (e.g., DFSR) using TI's StarterWare Code in ARM Cortex A-8 microprocessor (Sitara). Sitara (uP)  is part of a Texas Instrument Board called BagleBone Black (BBB).

To develop the software program, I started with the starter ware software package, developed for the BBB board by the manufacturer -TI. Code Composer Studio (Eclipse-based IDE) is used to build, compile, link, and load the program to onboard uP using JTAG interface. My program is written in C and arm-assembly. The code is compiled using the default compiler by TI.

As of now, I am unable to read any system-level registers (contain bit upset flags in Cache memory). 

For example, during enabling error correction in Cache memory, the lines below do not work -

 

MRC p15, #1, r0, c9, c0, #2 ; Read L2 Cache Auxiliary Control Reg into R0

MCR p15,#0x0,r1,c7,c5,#6 ; invalidate entire branch predictor array

 

I get the following error – ’outside program memory’

Any suggestions?”

Note: I can run regular algorithms/ calculations/ R/W to DDR using JTAG fine.


Mahmud

  • Hi Mahmud,

    Note the processor should be in a priviledged state to access these CP15 registers. This is the state of the A8 after completing the Starterware initialization routines.

    There is a Starterware API function for invalidating the entire branch predictor array. Please see <PDK>\packages\ti\starterware\soc\armv7a\gcc\cp15.S, CP15BranchPredictorInvalidate.

    I wasn't able to locate any Starterware routines for reading/writing the Data Fault Status Register or L2 Cache Auxiliary Control.

    I was able to write routines for reading the registers as follows:

    • Create new utils.S file. I used the cp15.S file as a template for this new file.
    • Add routines CP15DfsrRead() and CP15L2CacheAuxCtrlRead() to new file.
    • Add function prototypes & test calls for CP15DfsrRead() and CP15L2CacheAuxCtrlRead() at start of application. I used the gpio_app_led_blink Starterware example as my application.
    • Add utils.S to application build by adding this line to the makefile (<PDK>\packages\ti\starterware\examples\gpio\led_blink\Makefile)
      SRCS_ASM_COMMON = utils.S

    These new functions works as expected and don't throw any errors.

    @******************************************************************************
    @*                                  SYMBOLS
    @****************************************************************************** 
    
            .global CP15DfsrRead
            .global CP15L2CacheAuxCtrlRead
    
    @******************************************************************************
    @*                                 CODE SECTION
    @******************************************************************************
            .text
    
            @ This code is assembled for ARM instructions
            .code 32
    
    @******************************************************************************
    @*                                 ASSEMBLY ROUTINES
    @******************************************************************************     
    
    @*****************************************************************************
    @ This API reads the Data Fault Status Register.
    @*****************************************************************************
    CP15DfsrRead:
            MRC       p15, #0, r0, c5, c0, #0 @ Data Fault Status Register into R0
            BX        lr
    
    @*****************************************************************************
    @ This API reads the L2 Cache Auxiliary Control Reg.
    @*****************************************************************************
    CP15L2CacheAuxCtrlRead:
            MRC       p15, #1, r0, c9, c0, #2 @ Read L2 Cache Auxiliary Control Reg into R0
            BX        lr
    
        .end
    

    Regards,
    Frank

  • Dear Frank,


    Your solution worked. I was not using SDK RTOS packages before. It took me a while to install and run RTOS. I apologize for my late response.

    My sincere thanks to you for helping me out.

    Since you are an expert here, I would love to ask a few additional questions below

    1. Is there a way that I can directly read the cache (Level 1, Level 2, and Level3)?
    2. How do I run computational algorithm exclusively either in Integer or Neon core of Beagle Bone Black (AM3358).
    3. How do I transfer data from the beagle bone registers to my laptop during the program execution? During the program execution part is important.

    Only qualitative guidelines will also suffice considering I have asked you too many questions?

    Kind Regards,
    Mahmud Reaz

  • Hi Mahmud,

    Can you please open a new thread for these questions since they're unrelated to the original question? This makes it easier for other uses to track questions on responses on the e2e forum.

    Thanks,
    Frank