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Original question:

AM3874: Boot-behavior and clock subsystem (pcie / serdes)

AM3874: startup problem with a pciedevice

Chris haaf92
Prodigy 190 points
Part Number: AM3874
Other Parts Discussed in Thread: XIO2001

Hello,

 

There is still an issue regarding the startup of our system, when there is a pcie-device TI xio2001 (pcie/pci bridge) connected.

Also see ticket https://e2e.ti.com/support/processors/f/791/t/942634

A brief architecture of our system:

 

In the scope-picture we can see:

nGRST – indicates the internal Reset of the xio2001. It is only connected to capacitors.

nPCIeReset – this signal is controlled by the sitara. In this case we added a pulldown, so the signal is only released by the CPU

3V3 – this is our supply voltage, as you see it is stable

nPOR (PORz) – it is controlled by a voltage supply chip from power on and from a FPGA. We implement a watchdog in the FPGA, when the system is not starting

AM_CDCM_CE – is connected to the sitara and always stable

PCIeClock – unfortunately we can`t scope it well due to the sampling frequency.

 

When we want to read the pcie register the cpu stucks.

This problem is repeatable on some board very often (> 9 of 10 times) and on other boards (same hardware and software) the problem doesn’t occur.

We are booting from a spi flash

Thanks and regards

Chris

  • 0
    Prodigy 190 points

    Some additional information:

    We scoped the PCIeClock with a trigger on rising edge of pcie-reset. To make sure, that the input pins (especially the CE) of the CDCM-chip are stable we connected the signal on Vcc (3V3).

    Although we see a drop of the clock. Do you have an explanation?

  • 0 in reply to Chris haaf92
    TI__Mastermind 23125 points

    Chris, 

    Sorry for the extended delay in response. there were some mixed up in our assignment system. Not sure if you made any progress since your last post, if you still have board failures, I like to debug with you based on the following clarifications:

    1. What is the clock glitch period in last scope capture, starting from deassertion of the reset signal and check if the latency violated the PCIe spec. 

    2. Since the clock signal is generated from the CDCM, could it be that the XIO device caused noise on the clock?

    I saw there was a previous thread on the same topic, and will review the detailed debugs once you confirm back. 

    Jian