• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 102 subscribers
  • Views 206 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6548: About access time to MCU_MSRAM and DDR.

tomitama
Expert 1090 points
Part Number: AM6548
Other Parts Discussed in Thread: TMDX654IDKEVM, CLOCKTREETOOL

In the R core on TMDX654IDKEVM,
We are verifying the access time to MCU_MSRAM and DDR.

question 1
Please tell me about the theoretical value (MHz) at the time of Read / Write from R core to MCU_MSRAM and DDR when 400MHz is supplied to R core.

Below are additional questions.
Additional question 1
The access route from the R core to the MCU_MSRAM is
"R core → MCU_CBASS0 → MCU_MSRAM"
Are you sure?
Also, the access route to DDR is
"R core → MCU_CBASS0 → CBASS0 → NAVSS → MSMC → DDRSS"
Are you sure?

Additional question 2
I have confirmed it on ClockTreeTool (AM65xSR2.0).
0x00000001 in CTRLMMR_WKUP_MAIN_SYSCLK_CTRL
0x00008000 in WKUP_PLLCTRL0_PLLDIV1
Set, and
When 400MHz is supplied to MCU_R5_CORE0,
200MHz and 100MHz are supplied to MCU_MSRAM0.
Is it okay to understand that it operates at 200MHz when reading and writing data and at 100MHz when changing settings?

MCU_CBASS0 is supplied with 200MHz, 100MHz and 50MHz,
Does 200MHz and 100MHz apply to access to MCU_MSRAM0?

In addition to the above, is it okay to recognize that it operates at 200MHz when reading and writing from the R core to the MCU_MSRAM?

Best regards

  • 0
    Genius 5735 points

    Hello Tomitama,

    I've spent quite some time getting hold of these numbers and ended up measuring access latencies myself, see this thread: https://e2e.ti.com/support/processors/f/791/t/840395

    A TI employee eventually confirmed my numbers, so I'm guessing they're correct, but maybe someone from TI has new input on this issue.

    These are the numbers I ended up with (latency for reading a 32-bit word of data that ins't already in R5f caches)

    >>This leaves us with ~34 cycles for accesing MCU SRAM, ~104 cycles for accessing MSMC SRAM and ~146 cycles for accessing DDR RAM.

    Looking at the raw MHz numbers of the interconnect probably isn't going to help, since the architecture of the interconnect is undocumented, i.e. you don't know how many register stages there are inbetween.

    Regarding the access routes I sugesst you look into SPRACI6. That's the most complete description of the interconnects I could find.

    Regards,

    Dominic