TMS320C6657: CPU floating-point operation speed

The GMAC performance in the data sheet is based on raw performance of the DSP core when the code is pipelined across the the DSP instructions pipe.  The value provided by compiler may be slightly lower based on how the code is written, what optimization level is used, what is the location of the code and what memory latency it adds, etc

Please locate all code and data to L2 memory,  turn on L!P and L1D cache and select the -O3 option with the compiler. Make sure data is aligned to cache line boundary and use simple optimizations as indicated here to see highest performance from the core.

https://www.ti.com/lit/an/sprabg7/sprabg7.pdf?ts=1614879786100&ref_url=https%253A%252F%252Fwww.google.com%252F 

https://e2echina.ti.com/cfs-file/__key/telligent-evolution-components-attachments/13-101-00-00-00-00-45-48/Introduction-to-TMS320C6000-DSP-Optimization.pdf

The performance of the core is independently evaluated by BDTI and other customers. You can also check out core benchmarks here and refer to our DSP lib for performance entitlement techniques.

https://www.ti.com/microcontrollers-mcus-processors/processors/digital-signal-processors/core-benchmarks/getting-started.html 

https://www.ti.com/microcontrollers-mcus-processors/processors/digital-signal-processors/core-benchmarks/device-benchmarks.html 

Regards,

Rahul