Hi All,
Sorry to bother again - our product is now using this processor for mass production and it cannot be replaced/upgraded easily...
In OMAP35x technical reference manual, Table 17.54 said FCR_REG.TX_FIFO_CLEAR is a write-only register; when you set this bit to 0x1 it Clears the transmit FIFO and resets its counter logic to
0. Returns to 0 after clearing FIFO.
Since the manual also said FCR_REG is not readable(Section 17.5.1.1.2, step 5), then how may I tell if a TX FIFO reset request is finished?
- pxshu