We have some questions regarding the GPMC controller in the AM572 SOC.
The memory that is controlled by the GPMC (MRAM) is very slow compared to normal RAM. This is quite normal and nothing strange really. But we are seeing performance issues for the whole system when we write to this MRAM, since it keeps the whole L3 interconnect busy. Going through the technical reference manual it seems like there are some solutions for this problem. The first workaround is the FIFO in the GPMC which can cache writes but it is a bit small for us, only 16x32bits.
The next solution mentioned is a DMA which can be triggered by FIFO empty/low signals. So the DMA fetch from RAM/cache and writes to the FIFO only when there is space available. This will not stall the bus in the same way.
Our question is if the current GPMC driver for Linux supports this DMA mode? If so, are there any examples available? Alternatively any guidance that we can use to get this working in a proper way?