DRA829V: DRA829 Processor - EMIF interface - DDR Pin delay

Meenalochini D

Prodigy 150 points

Part Number: DRA829V
Other Parts Discussed in Thread: DRA829

Hi team,

We were using DRA829 processor and LPDDR4 interface for our design.

We would like to know the pin delay details for LPDDR4 routing and SI simulation.

Request you to provide the details.

Please share your recommendation for the DDR4 -Differential signal's "Min .line spacing, Primary gap & Neck gap " - spacing details.

Regards,

D.Meenalochini.

over 3 years ago

0 Kevin S over 3 years ago

TI__Mastermind 26455 points

Hi,

I am not sure whether I fully understand your question. However, there are delay and spacing requirements published in the Jacinto7 LPDDR4 layout guidelines document.

If you have not already, can you please review the Jacinto7 LPDDR4 layout guidelines to see if it answers your question?

https://www.ti.com/lit/pdf/spracn9

Thanks,
Kevin

0 Meenalochini D over 3 years ago in reply to Kevin S

Prodigy 150 points

Okay,will refer the guideline document

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DRA829V: DRA829 Processor - EMIF interface - DDR Pin delay