Processors forum - Recent Threads

SK-AM62-LP: SK-AM62-LP — AM62 SoC never starts, chip stays cold, all UARTs silent

Brian Johnson — Fri, 15 May 2026 23:54:05 GMT

Part Number: SK-AM62-LP
Other Parts Discussed in Thread: TPS65219

I'm attempting first boot on a new SK-AM62-LP (PCB rev PROC124E1) and the AM62 SoC never executes. The chip stays at ambient temperature regardless of boot configuration or power source, and all four UART channels are silent.

Hardware

- Board: SK-AM62-LP (PROC124E1)

- Host: macOS, serial monitor via tio at 115200 baud

- Power: USB-C PD via J13 from MacBook USB-C port (5V/3A). LD8 illuminated confirming PD contract.

- SD card: 64GB microSD, MBR partition table, p1 = 256MB FAT32 with prebuilt boot artifacts from TI Processor

SDK Linux 11.02.08.02 (tiboot3.bin, tispl.bin, u-boot.img, Image, k3-am62-lp-sk.dtb, uEnv.txt), p2 = ext4rootfs from tisdk-default-image-am62xx-lp-evm.rootfs.tar.xz

Boot mode switches

Per SPRUJ51A §2.19.2, Table 2-18/2-19/2-32 — uSD boot (MMC1), 25 MHz PLL:

- SW3: positions 1=ON, 2=ON, 3=OFF, 4=OFF, 5=OFF, 6=OFF, 7=ON, 8=OFF

- SW4: positions 1=OFF, 2=ON, 3=OFF, 4=OFF, 5=OFF, 6=OFF, 7=OFF, 8=OFF

Symptoms

- 4 LEDs illuminate on power-on (LD5, LD6, LD8, LD10)

- AM62 SoC is cold to the touch — not drawing current

- All four Tiva-C UART channels (/dev/tty.usbserial-102612400940 through ...943) silent at 115200, 9600, and 921600 baud

- Behavior identical with and without SD card inserted

- Behavior identical across all tested power sources: iPhone 5W USB-A, 5V/2.1A USB-A adapter, MacBook USB-C via J13

What I've ruled out

- Power delivery: LD8 lit, PD contract confirmed via J13. Mac USB-C port tested as clean 5V/3A PD source.

- UART channel: all four channels monitored, all silent

- Boot media: symptoms identical with SD absent — chip never starts regardless

- Boot mode switches: verified against SPRUJ51A §2.19.2 tables, settings correct for uSD/MMC1/25MHz

Key observation

A cold SoC indicates the AM62 is not executing at all — not even the boot ROM. If the ROM were running and failing to find a boot device, the chip would be warm and we would see UART output on WKUP_UART0. This symptom points to the SoC core rails not coming up (TPS65219 not sequencing), or a defective SoC.

Questions

1. Is there anything in the TPS65219 power sequencing that could prevent the AM62 core rails from enabling despite LD8 being illuminated?

2. Are there any known QC issues with this batch that could explain a cold SoC on a new board?

3. Can you advise on RMA/replacement options?

TMS320LF2407A: TMS320LF2407APGEA

Michael Nestor — Fri, 15 May 2026 19:50:08 GMT

Part Number: TMS320LF2407A

Where can we find information to confirm the following for TI part number TMS320LF2407APGEA. A customer is driving specific requirements for Assembly and Test in Phillipines and Wafer Fab in Dallas, but we are unsure how to confirm or guarantee that for ordering.

Assembly Site

Test Site

Wafer Fab Site

AM3352: AM335x DCAN Issue (tx; echo_skb is occupied)

Michael Rosen — Fri, 15 May 2026 18:34:20 GMT

Part Number: AM3352

We are running into an issue with a board in one of our products that uses an AM335x MPU to talk to peripheral devices over CAN (specifically the AM3352BZCZA60). Sometimes under heavy load on the CAN TX side (context: we are DFUing one of the peripheral devices via CANopen CiA 302, ie doing a block download, so something like 128 messages per block on the TX), we notice we are getting the following message from the DCAN driver before the TX side seems to stop working:

kernel: c_can_platform 481cc000.can can0: can_put_echo_skb: BUG! echo_skb 29 is occupied!

We are running a relatively recent version of the driver (6.1.46-ti-r19), is this a known software issue with this MPU/peripheral or if theres any errata on this part/this version of the DCAN that might cause this problem?

TDA4VH-Q1: appRtosTaskDelete() bug report

Nikita Yushchenko — Fri, 15 May 2026 17:52:45 GMT

Part Number: TDA4VH-Q1

Just faced an issue with j784s4 PSDK 11.2 (likely also on other versions and SoCs that use pdk).

Problem: got R5+safertos hangs short after clean termination of a task, via appRtosTaskDelete().

After a long debugging session, found that root cause is:

in appRtosTaskCreate(), the tsk is automatically registered in perfstats, via appPerfStatsRegisterTask(),
but this is not undone in appRtosTaskDelete(), resulting into a dangling task pointer inside perfstats,
later this is causing a crash.

Below is a patch adding reverse operation for appRtosTaskDelete(), that made the issue to no longer reproduce.

Date: Fri, 15 May 2026 18:48:07 +0200
Subject: [PATCH] app_utils: perfstat: survive after task termination

Since appRtosTaskCreate() autoimatically adds the created task to
perfstat, appRtosTaskDelete() shall remove it. Otherwise, a
dangling task pointer is left in perfstat, causing crashes.
---
 .../utils/perf_stats/include/app_perf_stats.h |  9 +++++
 .../utils/perf_stats/src/app_perf_stats_api.c |  6 +++
 .../perf_stats/src/app_perf_stats_api_x86.c   |  5 +++
 .../perf_stats/src/app_perf_stats_freertos.c  | 37 +++++++++++++++++++
 app_utils/utils/rtos/src/app_rtos_pdk.c       |  2 +
 5 files changed, 59 insertions(+)

diff --git a/app_utils/utils/perf_stats/include/app_perf_stats.h b/app_utils/utils/perf_stats/include/app_perf_stats.h
index 8ac585da1..a74a0604e 100755
--- a/app_utils/utils/perf_stats/include/app_perf_stats.h
+++ b/app_utils/utils/perf_stats/include/app_perf_stats.h
@@ -505,6 +505,15 @@ int32_t appPerfStatsPrintAll();
  */
 int32_t appPerfStatsRegisterTask(void *task_handle, const char *name);
 
+/**
+ * \brief Unregister a task from task load calculation
+ *
+ *        Must be called for terminated task
+ *
+ * \return 0 on success
+ */
+int32_t appPerfStatsUnregisterTask(void *task_handle);
+
 /**
  * \brief De-Initialize perf statistics collector module
  *
diff --git a/app_utils/utils/perf_stats/src/app_perf_stats_api.c b/app_utils/utils/perf_stats/src/app_perf_stats_api.c
index e1138f61f..fed4d0d02 100644
--- a/app_utils/utils/perf_stats/src/app_perf_stats_api.c
+++ b/app_utils/utils/perf_stats/src/app_perf_stats_api.c
@@ -685,6 +685,12 @@ int32_t appPerfStatsRegisterTask(void *task_handle, const char *name)
     /* NOT supported for LINUX */
     return -1;
 }
+
+int32_t appPerfStatsUnregisterTask(void *task_handle)
+{
+    /* NOT supported for LINUX */
+    return -1;
+}
 #endif
 
 void appPerfPointSetName(app_perf_point_t *prm, const char *name)
diff --git a/app_utils/utils/perf_stats/src/app_perf_stats_api_x86.c b/app_utils/utils/perf_stats/src/app_perf_stats_api_x86.c
index 523f21058..e1fd20316 100644
--- a/app_utils/utils/perf_stats/src/app_perf_stats_api_x86.c
+++ b/app_utils/utils/perf_stats/src/app_perf_stats_api_x86.c
@@ -125,6 +125,11 @@ int32_t appPerfStatsRegisterTask(void *task_handle, const char *name)
     return 0;
 }
 
+int32_t appPerfStatsUnregisterTask(void *task_handle)
+{
+    return 0;
+}
+
 void appPerfPointSetName(app_perf_point_t *prm, const char *name)
 {
 }
diff --git a/app_utils/utils/perf_stats/src/app_perf_stats_freertos.c b/app_utils/utils/perf_stats/src/app_perf_stats_freertos.c
index 374f322f9..d0b7825ff 100644
--- a/app_utils/utils/perf_stats/src/app_perf_stats_freertos.c
+++ b/app_utils/utils/perf_stats/src/app_perf_stats_freertos.c
@@ -723,6 +723,43 @@ int32_t appPerfStatsRegisterTask(void *task_handle, const char *name)
     return status;
 }
 
+int32_t appPerfStatsUnregisterTask(void *task_handle)
+{
+    app_perf_stats_obj_t *obj = &g_app_perf_stats_obj;
+    int32_t status = -1;
+    uint32_t idx;
+
+    if (1U == g_perf_stats_load_update_enable)
+    {
+        appPerfStatsLock(obj);
+
+        for (idx = 0; idx < obj->num_tasks; idx++)
+        {
+            if (obj->task_handle[idx] == task_handle)
+            {
+                status = 0;
+                break;
+            }
+        }
+
+        if (status == 0)
+        {
+            for (idx++; idx < obj->num_tasks; idx++)
+            {
+                obj->task_handle[idx - 1] = obj->task_handle[idx];
+                memcpy(obj->task_name[idx - 1], obj->task_name[idx], APP_PERF_STATS_TASK_NAME_MAX);
+                obj->taskLoad[idx - 1] = obj->taskLoad[idx];
+            }
+
+            obj->num_tasks--;
+        }
+
+        appPerfStatsUnLock(obj);
+    }
+
+    return status;
+}
+
 void appPerfStatsHwaResetLoadCalc(app_perf_hwa_id_t id)
 {
     app_perf_stats_obj_t *obj = &g_app_perf_stats_obj;
diff --git a/app_utils/utils/rtos/src/app_rtos_pdk.c b/app_utils/utils/rtos/src/app_rtos_pdk.c
index 994b78285..592d3fe42 100755
--- a/app_utils/utils/rtos/src/app_rtos_pdk.c
+++ b/app_utils/utils/rtos/src/app_rtos_pdk.c
@@ -271,6 +271,8 @@ app_rtos_status_t appRtosTaskDelete(app_rtos_task_handle_t *handle)
 
     if ((NULL != handle) && (*handle != NULL))
     {
+        (void)appPerfStatsUnregisterTask(*handle);
+
 /* LDRA_JUSTIFY_START
 <metric start> branch <metric end>
 <justification start> APP_UTILS_BRANCH_COVERAGE_RTOS_PDK_UBR002
-- 
2.47.3

J784S4XEVM: Issue with GPTP packet in A72 QNX

Manan Bhatt — Fri, 15 May 2026 16:00:36 GMT

Part Number: J784S4XEVM

Hi ,

We initilizing ETHFW in Maindomain R5F2_0 and We have enable the GPTP in r5f .

we are able to ping QNX A72 and Host response also fine .

We have configure ENET_MAC_PORT_2 for GPTP. This same port is used during initilization of ETH FW config.

QNX A72 side we are initilizaing io packet with below argument but when we checking PC, packets are not present.

We are using SDK version 9.2.0.5

io-pkt-v6-hc -d cpsw9g ptp=1,verbose=1 -i2 prefix=/alt2 -ptcpip

ptpd-avb -CWKLb an0 &

tcpdump -i an0 -e ether proto 0x88f7

AM625: M4 using GPIO and peripheral on main domain

ali joubir — Fri, 15 May 2026 15:02:08 GMT

Part Number: AM625

Hi TI team,

I am working on an AM62x-based design

From the AM62x datasheet, I see that many peripherals are separated by domain:

MAIN domain: UARTx, I2Cx, SPIx, GPIOx, etc.
MCU domain: MCU_UART0, MCU_I2C0, MCU_SPI0, MCU_GPIO0, etc.
WKUP domain: WKUP_UART0, WKUP_I2C0, WKUP_GPIO0, etc.

I would like to clarify the expected access model for the M4F.

Questions:

Can the AM62x M4F access and use MAIN-domain peripherals such as UART, I2C, SPI, and GPIO?
Can the AM62x M4F access and use WKUP-domain peripherals?
If yes, are MAIN-domain peripherals supported from the M4F in interrupt mode, or only polling mode?
For GPIO pinmux and ownership, is the configuration/control handled per individual GPIO pin or per GPIO bank? For example, if the M4F uses GPIO0 from a given MAIN-domain GPIO bank, can Linux/A53 still use GPIO1 from the same bank independently, or does the whole GPIO bank need to be assigned to one processor/domain?

AM62A-PET-CALC: Regarding Confirmation on SDK build for CAN Implementation

Undali Muniranga — Fri, 15 May 2026 12:28:50 GMT

Part Number: AM62A-PET-CALC

Hello Team,

Currently we are using AM62A SDK Versdion 9.2 for Evaluation board.

Due to git related errors mentioned in the ticket: AM62A-PET-CALC: Build Issue With While building AM62A SDK 9.2 Version - Processors forum - Processors - TI E2E support forums we are not able to build the SDK.

So, we are planning to Implemennt CAN on mentioned board. currently we are using Pre-built images for booting.

So whether building the SDK is mandatory or Just imeplement the CAN Source code and compile the source code and flash and test is sufficient?
if prebuilt images are sufficient and kindly provide the steps:

1) How to build the CAN source code

2)Where and which files need to copy on SD

Kindly reuesting to check and please let me know!

You cupport is highly appreciated!

Thanks & Regards

Undali Muniranga

DRA829J-Q1: Trigger a SW interrupt to R5F (MCU DOMAIN) from A72 (MAIN domain) ?

AnBer — Fri, 15 May 2026 11:54:35 GMT

Part Number: DRA829J-Q1
Other Parts Discussed in Thread: DRA829J

Team,

On DRA829J is it possible to route the Software interrupts from MAIN to MCU?
The concrete use case is for MCSPI2/MCSPI4:
Can I trigger the R5F MCU from the A72 core using software interrupt (via the interrupt aggregator)?

-Apparently SciServer seems to be using a comparable mechanism.
The MAIN domain navigator send requests that are routed to R5F MCU using specifc IRQ lines.
IRQ 71 and 73 seems to be used for this mechanism:
TISCI server intergation in autosar - www.ti.com/.../spracy6

-Also according to the below E2E some GPIO in MAIN domains seems to be accesible on the MCU R5F domain.
Do we have a code example showing those GPIOs trigering an interrupt on the MCU R5F domain?
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1199356/dra829j-gpio-configuration-inside-mcu-domain

Thanks in advance,

Anthony

AM62A1-Q1: Regarding Rpmsg buffer size

Sushma Hiremath — Fri, 15 May 2026 10:37:31 GMT

Part Number: AM62A1-Q1

The maximum allowed size for rpmsg buffer is 512 but In CCS 20 version, in syscfg.c file I can provide upto 1152 bytes. why CCS has option to increase the size more than wwhat is allowed?

TMDS64EVM: ICSSG switch mode initialization issues

Mateusz Szalkowski — Fri, 15 May 2026 09:50:07 GMT

Part Number: TMDS64EVM
Other Parts Discussed in Thread: AM6442

Hello,

I have a problem with proper initialization of ICSSG two port ethernet switch mode. I'm using commands from documentation for latest SDK. One thing I cannot overcome is dropping multicast packets, SMV traffic to be specific (ether type 0x88BA). My setup is as below:

PC <-> EVM (switch mode) <-> AM6442 custom board

Custom board is sending PTP packets, SMV packets and as an additional test ICMP ping. If I strictly follow switch mode configuration order on EVM described in documentation (with physical interfaces already up):

ip link add name br0 type bridge
ip link set dev eth1 master br0
ip link set dev eth2 master br0
ip link set dev br0 up
bridge vlan add dev br0 vid 1 pvid untagged self

and watch traffic on Wireshark on PC, I can see different behavior in differenct scenarios:

enable switch mode with PC on EVM eth1, custom board on EVM eth2 (already connected on boot) - in this case I can see SMV, PTP ICMP traffic is forwarded both ways, also after switching cables on eth1 and eth2 ports
enable switch mode with custom board on EVM eth1, PC on EVM eth2 - first ~20 SMV packets forwarded, then all SMV dropped, PTP and ICMP forwarded properly
configure switch mode and connect eth afterwards - all SMV dropped, PTP and ICMP forwarded properly

I tried playing with VLAN configuration, FDBs, MDBs, multicast flooding and cut through forwarding, but these setting didn't seem to have any influence on filtering once SMV dropping is noticed.

Another thing is if after configuring switch mode and noticing SMV being dropped I first disable both physical interfaces and then bring them back up (which causes ICSSG firmware to reload), I can see that whole traffic including SMV is being forwarded but only from port that was brought up later to the one that was brought up first, to be specific.:

ifconfig eth1 down
ifconfig eth2 down
ifconfig eth1 up
ifconfig eth2 up

will cause only forwarding traffic from eth2 to eth1. EVM itself still responds to ping on both ports, but both devices connected to EVM can't reach each other.

I see this behavior of switch mode on both EVM board running image from 12.0 SDK and custom AM6442 board with Yocto build using kernel 6.18.13 and icssg0 instead of icssg1 used by EVM.

The main question is do I miss something in the configuration of switch mode? Is it ICSSG binary or driver bug? Also which behavior is expected, dropping multicast traffic or forwarding it? Any other think I could test or check to find a root cause of these differences?

Best regards,
Mateusz

AM62A7-Q1: How to modify the DDRSS0 freq to 1525MHz

Dejin ZHENG — Fri, 15 May 2026 07:51:36 GMT

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi TI experts,

We are trying to change the DDRSS0 freq from 1600MHz to 1525MHz on the AM62A7-Q1 platform.
:The LPDDR4 memory is NT6AN256T32AC-J1H.
:SDK ver 11.01

We have tried the following steps:

1) We used the TI SysConfig Tool to change the FSP2 Freq from 1600 to 1525.

Then, we placed the generated board_ddrReginit.h file into the mcu_plus_sdk/source/drivers/ddr/v1/soc/am62ax/ directory, recompiled the software, and flashed it onto the board.
When we used k3conf dump clock to check the DDR clock, it showed:
DEV_DDR32SS0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 762500000
However, when we measured the waveform of the DDR0_CK0/DDR0_CK0_N pins using an oscilloscope with a differential probe, we found that the actual physical clock is still at 1600MHz.

2) Based on the steps above, we made additional code modifications:
In mcu_plus_sdk/source/drivers/ddr/v1/soc/am62ax/ddr_soc.h: Changed #define DDR_MHz (1600U) to (1525U)
In mcu_plus_sdk/source/drivers/ddr/v1/soc/am62ax/ddr_soc.c: Changed #define MAIN_PLL12_OFC1_FBDIV 64 to 61

We recompiled the software and flashed it to the board again. However, measuring the DDR0_CK0/DDR0_CK0_N pins with the oscilloscope differential probe still shows the clock at 1600MHz.

Could you please help check if there are any other places in the software that need to be modified to make this take effect?

Thanks in advance!

DRA821U: Support Required for PCIe SERDES Configuration on J7200 SDK 11.02.00.04

Ashwini A — Fri, 15 May 2026 07:25:24 GMT

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Hi Team,

We are using PROCESSOR-SDK-LINUX-J7200 version 11.02.00.04 for a DRA821 custom board.

We are trying to enable PCIe using SERDES0 Lane0 and Lane1 and the PCI device should receive 100MHz reference clock from the internal SERDES clock source.

Below changes for PCI were added in custom dts by including k3-j7200-main.dtsi:

&serdes_refclk {
clock-frequency = <100000000>;
};

&serdes_wiz0 {
status = "okay";
};

&serdes0 {
status = "okay";

serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
};

&pcie1_rc {
status = "okay";
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};

&serdes_ln_ctrl {
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>,
<J7200_SERDES0_LANE1_PCIE1_LANE1>,
<J7200_SERDES0_LANE2_IP3_UNUSED>,
<J7200_SERDES0_LANE3_IP4_UNUSED>;
};

After booting, below logs are observed:

dmesg | grep -i "pci"

[ 0.582079] PCI: CLS 0 bytes, default 64
[ 17.166116] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 17.173621] j721e-pcie 2910000.pcie: IO 0x4100001000..0x4100100fff -> 0x0000001000
[ 17.181711] j721e-pcie 2910000.pcie: MEM 0x4100101000..0x41ffffffff -> 0x0000101000
[ 17.189797] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 18.201861] j721e-pcie 2910000.pcie: PCI host bridge to bus 0000:00
[ 18.208179] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 18.213658] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff] (bus address [0x1000-0x100fff])
[ 18.222686] pci_bus 0000:00: root bus resource [mem 0x4100101000-0x41ffffffff] (bus address [0x00101000-0xffffffff])
[ 18.233211] pci 0000:00:00.0: [104c:b00f] type 01 class 0x060400 PCIe Root Port
[ 18.240520] pci 0000:00:00.0: PCI bridge to [bus 00]
[ 18.245476] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
[ 18.251559] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 18.258339] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]
[ 18.266134] pci 0000:00:00.0: supports D1
[ 18.270136] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 18.277060] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 18.285156] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 18.291773] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 18.296736] pci_bus 0000:00: resource 4 [io 0x0000-0xfffff]
[ 18.302382] pci_bus 0000:00: resource 5 [mem 0x4100101000-0x41ffffffff]
[ 18.309052] pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22
[ 18.315861] pcieport 0000:00:00.0: PME: Signaling with IRQ 534
[ 18.321888] pcieport 0000:00:00.0: AER: enabled with IRQ 534

PCIe root port is getting initialized, however connected PCIe endpoint device is not getting detected.

Request your support to provide the correct DTS configuration required for:

PCIe x2 using SERDES0 Lane0 and Lane1
Internal 100MHz SERDES reference clock configuration
Required WIZ/PLL clock node configuration for SDK 11.02.00.04

Thanks & Regards,
Ashwini

DRA829V: MCU-ONLY mode with MCSPI0, MCSPI1 and MCSPI2 dependent on Main domain

Jakob Bleickert — Fri, 15 May 2026 06:50:38 GMT

Part Number: DRA829V

Dear TI team,

In MCU-ONLY mode, we would like to use MCSPI0, MCSPI1 and MCSPI2, which are dependent on Main domain. According to the TRM, MCSPI requires:

LPSC7
PLL0_HSDIV5
PLLCTR0

These are only available for Main domain ON and I suspect that we need to transition to ACTIVE mode. How can we accomplish that and run MCSPI?

Thanks a lot for your help.

Best regards,
Jakob

TDA4VH-Q1: [J784S4] Recommended Kernel/DTB Configuration for ADAS POC: Vision Apps + Radar Fusion with 60ms Latency Target

VADDEPALLY NIVAS NETHA — Fri, 15 May 2026 06:10:16 GMT

Part Number: TDA4VH-Q1

Description:
We are developing an AEBS (Advanced Emergency Braking System) POC on the J784S4 EVM. Our goal is to achieve an end-to-end latency of 60-70ms for a fused 1 Radar + 1 Camera pipeline.

While the accelerators (DSPs/C7x) are functional via vision-apps, we are stuck in a "rabbit hole" of display and memory conflicts. We need a "Golden Configuration" recommendation for an ADAS-centric
setup.

Current Technical Blockers:
1. Memory Overlap: When applying k3-j784s4-edgeai-apps.dtbo to enable the display and OpenVX acceleration, we encounter a RESERVED MEM: OVERLAP DETECTED! error at 0xaf000000. This appears to be a
conflict between the ethfw (virtual switch) and the vision-apps DMA memory map.
2. DRM Master Conflicts: Even when attempting to use the Edge AI overlays, background services like weston or emptty are initializing and grabbing DRM Master privileges. This prevents TIOVX/OpenVX
nodes from writing directly to the display (/dev/dri/cardX), leading to permission denied or "cannot find crtc" errors.
3. Boot Persistence: Our uEnv.txt settings for name_overlays are frequently ignored or overridden by default U-Boot environments, making the setup unstable.

Requirements for POC:
* Pipeline: Camera (JPG/NV12) + Radar Data -> TIOVX (DSPs/C7x) -> Display Output (Split-screen).
* Display: Raw KMS/DRM access for OpenVX display nodes without interference from a Window Manager.
* Networking: Standard Linux Ethernet is sufficient; we do not strictly require the R5F-based ethfw virtual switch if it frees up memory for Vision Apps.

Request for Guidance:
1. DTB/Overlay Strategy: What is the recommended combination of .dtb and .dtbo files for a J784S4 ADAS application that requires both Vision Apps (TIOVX) and direct DRM display output?
2. EthFW Deactivation: What is the "TI-intended" way to completely disable the ethfw memory reservations to allow the vision-apps memory map to take precedence without overlaps?
3. Kernel Config: Are there specific CONFIG_DRM_TIDSS or CONFIG_REMOTEPROC flags we should prioritize in a custom kernel build to ensure the display is ready for OpenVX at boot?
4. Display Management: What is the best practice for disabling weston/emptty permanently in the SDK 11.x filesystem to ensure the display remains available for accelerated user applications?

We are looking for a stable starting point (U-Boot env, DTB list, and Kernel config) that supports the high-performance requirements of an ADAS pipeline.

SK-AM62P-LP: Android adding DSS1 for LVDS and DSS0 Hdmi sharing accross A53 and WKUP R5

Shanooj P P — Fri, 15 May 2026 05:52:35 GMT

Part Number: SK-AM62P-LP

HI,

We are working with the following setup:

Processor SDK Android for AM62Px: 11_00_01
Android Version: 16
Kernel Version: 6.12

Current display configuration:

DM core application uses HDMI DSS0
Android uses LVDS -DSS0 *removed hsmi noed from the dtb)

With this setup:

LVDS displays Android UI
HDMI displays telltales from the DM core application

Now we would like to share the HDMI display with Android as well.

I have a few questions regarding the DSS/display architecture:

Is it possible to switch the display assignment such that:
- DSS0 HDMI is used by Android
- DSS1 LVDS is also used by Android
while still allowing the DM core application to use HDMI?
Is it possible for both cores to access both displays simultaneously? For example:
- DM core has access to both HDMI and LVDS
- Android also has access to both HDMI and LVDS
If simultaneous access is not supported, what is the recommended approach for sharing or dynamically switching display ownership between Android and the DM core?

Could you please suggest the supported architecture or recommended implementation approach for this use case?

Thanks,

TDA4VH-Q1: R5F vs C7100 vs C6678 vs A72 performance comparison for math operations in double-precision

Y. Bas — Fri, 15 May 2026 05:36:03 GMT

Part Number: TDA4VH-Q1

Hi,

As a follow-up to the question discussed in the TI E2E thread below:

TI E2E forum thread

could you also provide some performance metrics or relative performance expectations for non-vectorizable scalar double-precision arithmetic operations on the following cores?

C6678 (C66x DSP)
C7120 / C71x DSP
Cortex-R5F
Cortex-A72

More specifically, I am referring to ordinary scalar FP64 operations such as:

add/subtract
multiply
divide
dependency-heavy arithmetic chains
small-loop computations that cannot be efficiently vectorized

In such workloads, is it normal to observe similar performance between the C6678 and the C7120/C71x cores?

Since the C71x architecture appears to achieve its main performance gains through SIMD/vector processing and high throughput parallelism, I would like to better understand the expected behavior for scalar double-precision workloads where vectorization is not effective.

Best regards

CCSTUDIO: Not able to download CCS 10.4 on MacOS

Henry Huynh — Fri, 15 May 2026 01:03:43 GMT

Part Number: CCSTUDIO

So I tried downloading both the offline and the on-demand(web) installer but it wont open on my mac. When i finish downloading the file and open the dmg then tried to open the ccs_setup_10.4.0.00006 but nothing happens. I am not able to close it either, mac says its open and running but nothing pops up, I can only close it by force close.

AM69: AM69 and TDA4VH - ARM cores accesibility

Himanshu Devi — Thu, 14 May 2026 22:20:20 GMT

Part Number: AM69
Other Parts Discussed in Thread: TDA4VH,

Hello,

Could you please confirm the staus of cores accessible on AM69 and TDA4VH parts?

I am looking to access R5F cores on Main and MCU island, specifically. Please also let me know the staus (locked/unlocked) for DSP and A72 cores as well.

Regards,

TMDS64EVM: PRU RGMII receive packets data corrupted?

Seth Appleman — Thu, 14 May 2026 20:25:50 GMT

Part Number: TMDS64EVM

I am sending UDP packets from my laptop to the TMDS64EVM via the ICSSG1 RJ45 Connector on the board. I am running code on the ICSSG1_PRU0 core to capture the ethernet traffic and send it to the R5F core 0 via shared memory.

After setting up my clocks (Core clock, IEP clock, RGMII 250 MHz clock) and setting my pinmux (enabling RGMII RX and TX pins), I enable the board MDIO.

I then initialize the RGMII interface as follows:

ICSSG1_MII_G_RT_ICSS_G_CFG = 0x00010228 (SGMII_MODE = 1, RTU_PRU_PSI_SHARE_EN = 1, MII1_MODE = 1, MII0_MODE = 1)
ICSSG1_MII_RT_RXCFG0 = 0x17 (RX L2 FIFO enabled, RX_MUX_SEL=0, RX_CUT_PREAMBLE=1, RX_DATA_RDY_MODE_DIS=1, RX_ENABLE=1)
ICSSG1_MII_RT_RXCFG1 = 0x1F (RX L2 FIFO enabled, RX_MUX_SEL=1, RX_CUT_PREAMBLE=1, RX_DATA_RDY_MODE_DIS=1, RX_ENABLE=1)
ICSSG1_GPCFG0_REG = 0x08000003 (PR1_PRU0_GP_MUX_SEL = 2 (MII mode), PRU0_GPI_MODE= 3 (MII RT mode))
ICSSG1_MII_G_RT_ICSS_G_CFG = 0x0001022B (SGMII_MODE = 1, RTU_PRU_PSI_SHARE_EN = 1, MII1_MODE = 1 (RGMII), MII0_MODE = 1 (RGMII), RX_L2_G_EN = 0 (disable new RX L2 mode for nonEther-CAT protocols), TX_L2_EN = 1 (enable TX L2 FIFO), TX_L1_EN = 1 (enable TX L1 FIFO))
ICSSG1_MII_G_RT_RGMII_CFG = 0x004400BB (RGMII1_FULLDUPLEX_IN = 1 (full duplex override), RGMII1_GIG_IN = 0 (100 Mbs), RGMII0_FULLDUPLEX_IN = 1 (full duplex override), RGMII0_GIG_IN = 0 (100 Mbs))
ICSSG1_MII_RT_RX_FRMS0 = 0x6 (min frame count to 6 bytes (2 PE + 4 payload bytes) on both ports)
ICSSG1_MII_RT_RX_FRMS1 = 0x6 (min frame count to 6 bytes (2 PE + 4 payload bytes) on both ports

Then I initialize my task manager as follows:

ICSSG1_PRU0_TASKS_MGR_GLOBAL_CFG = 0 (disable all tasks)
ICSSG1_PRU0_TASKS_MGR_GLOBAL_CFG = 0x79 (TASK_MGR_MODE = 1 (RXTX mode), enable TS1_S4, TS1_S3, TS1_S2, TS1_S1)
ICSSG1_PRU0_TASKS_MGR_TS1_PC_S1 = &Rx_BK1
ICSSG1_PRU0_TASKS_MGR_TS1_PC_S2 = &Rx_BK2
ICSSG1_PRU0_TASKS_MGR_TS1_PC_S3 = &Rx_BKn
ICSSG1_PRU0_TASKS_MGR_TS1_PC_S4 = &Rx_EOF
ICSSG1_PRU0_TASKS_MGR_RX_CFG = 0x7FFF (BKN_SIZE = BK2_SIZE = BK1_SIZE = 31)

Finally I enable the task manager and enter a loop to wait for received packet data.

For the ethernet receive functions configured as event handlers for received bytes per the task manager setup above (Rx_BK1,Rx_BK2,Rx_BKn,Rx_EOF), each calls the same routine to actually pull the data off of the RX L2 FIFO [This allowed me to see each event firing individually, but use a common block of code to actually pull data from the FIFO – each of those 4 routines sets some parameters that the assemble code uses to know which FIFO bank to read from, our what shared memory address to write data to after receiving]:

ethRx:
       ; save registers to scratch bank
   xout 10, &r0, 27*4
   ; store shared memory buffer address from calling routine for XFR2VBUS write
   mov r10, r15
   ldi r11, 0
   ; set 32 byte mode for xf2vbus
   ldi r17.b3, 0

   ; check if its time to process bank0 or bank 1 (based on parameter from calling routine)
   qbeq bank1, r14, 0xB1
bank0:
   ; capture data words from bank0
   xin 20, &r2, 32
   qba dma
bank1:
   ; capture data words from bank1
   xin 21,& r2, 32

dma:
   ; check status of xf2vbus write command
   xin 0x62, &r20.b0, 1
   ; loop if active
   qbeq dma, r20.b0, 1

   ; write to shared memory buffer (32 bytes data, 8 bytes dest addr)
   xout 0x62, &r2, 40
rx_done:
   ; done if not EOF frame (parameter passed from calling routine)
   qbeq done, r16, 0x0
eof_flag:
       ; reset RX (b18); clear EOF(b22) and rx_error_clr (b23)
   or r31.b2, r31.b2, 0xF4
done:
   ; restore r0-r26 from Sratch Pad Bank 0
   xin SCRATCH_BANK0_XID, &r0, 27*4
   ; return
   jmp                       r3.w2

When I send a packet from my laptop I can monitor the transmitted packet via Colesoft packet builder:

Which matches what I see transmitted per wireshark:

Having set the RX_CFG parameter CUT_PREAMBLE to 1, I expect that the received data in my packet processing code will not contain the preamble of SFD bytes, so the first bytes I should see are the destination addresses in the UDP packet. However, this is the first data that I transfer over with my XIN command (captured via the UNEXPECTED event trigger routine, Rx_EOF, NOT Rx_BK1):

Running again, I capture:

Sending the same identical packet results in completely different “garbage” data for every time I see data triggered as being received in my RX FIFO. I am stumped and need help understanding how to debug.

So lots of questions here. Not sure if I am setting up the RGMII correctly, not sure if I am setting the task manager settings correctly. I think that I am properly popping data off of the R2 FIFO, but can’t really understand why the data looks so terrible, and is inconsistently so.

This is a large issue I need to decipher so appreciate help.

SM320C50-EP: SM320C50-EP - SM320C50PGEA57EP

venmeganathan G — Thu, 14 May 2026 17:30:58 GMT

Part Number: SM320C50-EP

Do you have any replacement part for SM320C50PGEA57EP or SM320C50PGEA57L3.

J784S4XEVM: Configure PMIC to reset on error pin

Jim Zhang — Thu, 14 May 2026 15:15:35 GMT

Part Number: J784S4XEVM

J784S4 MAIN domain ESM has error pin AM34, SOC_SAFETY_ERROR. Possible to configure the PMIC to reset on single domain only like domain0 ? If yes, which core should configure it? any example ?

CODECOMPOSER: No Device and Board for DRA821U in Code composer

P B — Thu, 14 May 2026 14:34:24 GMT

Part Number: CODECOMPOSER
Other Parts Discussed in Thread: DRA821U, J721EXCPXEVM

I'm trying to create a new project for DRA821U in CodeComposer (the one based on VSCode)

When I try to create a new project and select "Device and Board" to "DRA821U" there is not available board / devcice to select in other windows.

In this main window I can only see "Select a Device or Board from the filter at the top or change your selection"

The same happens for "Jacinto™ 7 common processor board (J721EXCPXEVM)"

How can I fix this?

Is CodeComposer designed for CPU debugging? If so - what debugger should I use?

AM623: AM6234 panel blue line when displaying grayscale picture

Daniel Cheng1 — Thu, 14 May 2026 14:05:19 GMT

Part Number: AM623

Hi Expert,

We are encountering an issue on the AM6234 platform where a single blue line appears on the display, but only when displaying grayscale images. This artifact does not appear under any other conditions or with colored content.

We suspect the root cause may be related to the panel-timing configurations. In our Device Tree Source (DTS), we are currently using the timings defined for the at070tn92 panel.

DTS part

panel {

compatible = "innolux,at070tn92", "panel-dpi";

power-supply = <&vcc_3v3_sys>;

backlight = <&lcd_bl>;

port {

panel_in: endpoint {

remote-endpoint = <&dpi1_out>;

};

We have attempted to modify or verify the configurations within the kernel source at: linux-11.01.05/drivers/gpu/drm/panel/panel-simple.c

We are attempting to adjust the pixel data sampling edge to resolve a grayscale artifact. We modified the bus_flags in the driver (panel-simple.c) as follows:

DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
OR
DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE

Observation: Despite these changes, we observed no change in the actual waveform.

As shown in the attached comparison:

The top image (red box) represents our expected waveform (proper alignment between the clock and data signals).
The bottom image shows the actual waveform currently generated by the AM6234.

Questions:

Are there other synchronized settings or registers that must be adjusted alongside bus_flags for these changes to take effect on the AM6234?
Why is the change in the driver code not reflecting in the physical output waveform?

Thanks

Daniel

DRA821U: Documentation for custom board bring up

P B — Thu, 14 May 2026 13:44:43 GMT

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Is there any documentation / guide / video / whatever regarding the complete bring-up of custom board based on DRA821?

I would be grateful for any recommendation.

AM62P: No able to configure ethernet using MCU

Patel Jayesh — Thu, 14 May 2026 13:15:04 GMT

Part Number: AM62P
Other Parts Discussed in Thread: UNIFLASH

I am trying to run UDP with the help of MCU R5 on the board, i am following the MCU+SDK guide and i have successfully ran the Hello world program,for the start i am using the prebuilt example and for that i am following https://software-dl.ti.com/mcu-plus-sdk/esd/AM62PX/12_00_00_27/exports/docs/api_guide_am62px/EXAMPLES_ENET_LWIP_CPSW.html but i am not able to get the output show in the end infact i am not able to get anything on the CCS console, i am only getting this as output

WKUP_R5FSS0_0: ***WARNING: Please close all Memory Browser Windows before attempting to initialize DDR with GELs
WKUP_R5FSS0_0: Running from R5
WKUP_R5FSS0_0:

DDR not initialized with R5 connect.

Go to menu Scripts --> AM62 DDR Initialization -> AM62P_DDR_Initialization_ECC_Disabled to initialize DDR.

====

WKUP_R5FSS0_0:
WKUP_R5FSS0_0: DDR programming has already been attempted.
WKUP_R5FSS0_0: DDR Initialization GEL script is being skipped...
WKUP_R5FSS0_0:

Please Help me out to run this example program so that i am able to run my intended UDP program