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LMX8410L: Homodyne IQ output "hopping" when using the DIV2 Quadrature Generator

Part Number: LMX8410L
Other Parts Discussed in Thread: LMX2594

When setting the LO below 7500MHz, I'm seeing significant jumps in the IQ output between frequencies (custom board).  These jumps are random and will change frequencies on subsequent sweeps (as you can kind of see here).  If the jumps occurred throughout the entire bandwidth I'd start to suspect my ADC or backend processing, but the fact that it always settles out prior to the 7500MHz mark makes me start to suspect an issue with the DIV2 Quadrature generator.  I've used the TICS Pro tool to setup my registers and I'm copying it's suggested register write order on the frequency change, but with no luck.  I'm waiting until the VCO locks before I start my readings, so it shouldn't be an issue with an unstable output.  Increasing my dwell time on each frequency (3ms-12ms) doesn't change the output at all.  

Any suggestions on what I'm doing wrong?  I suspect that it's a simple register issue somewhere, but the documentation for this device is spotty at best.  

  • Hello Raymond,

    It sounds like you are using the internal synthesizer for your LO generation. Are you sure the internal path is being selected, and you're not trying to source the LO externally? It's possible the VCO will still feed through the mux with no signal present on the LO pins, even at reduced amplitude; this would degrade the consistency of the divider output and could cause issues with the IQ phase precision.

    What is the y-axis on the graph above? I'm guessing green and blue correspond to I and Q outputs (or vice versa)?

    Can you upload the TCS file you're using to generate your settings?

    Regards,

    Derek Payne

  • 0172.HexRegisterValues.txt
    R127 (INIT1)	0x7F0003
    R6 (INIT2)	0x060100
    R127	0x7F0000
    R126	0x7E8000
    R125	0x7D0000
    R124	0x7C0000
    R123	0x7B0000
    R122	0x7A0000
    R121	0x790000
    R120	0x780000
    R118	0x760000
    R117	0x7500C0
    R116	0x740000
    R115	0x730F00
    R114	0x720000
    R113	0x710000
    R112	0x700000
    R111	0x6F00B7
    R110	0x6E0100
    R109	0x6D0000
    R108	0x6C0000
    R107	0x6B0000
    R106	0x6A0000
    R103	0x672C00
    R102	0x660000
    R101	0x650002
    R100	0x640002
    R99	0x630000
    R98	0x620000
    R97	0x610000
    R96	0x609218
    R95	0x5F0000
    R94	0x5E8080
    R93	0x5D0000
    R88	0x580000
    R87	0x570000
    R86	0x560000
    R85	0x550000
    R84	0x541900
    R83	0x536A20
    R82	0x520A23
    R81	0x510310
    R80	0x500009
    R79	0x4F0040
    R78	0x4E0064
    R77	0x4D0000
    R76	0x4C000C
    R75	0x4B0800
    R74	0x4A0000
    R73	0x49003F
    R72	0x480001
    R71	0x470081
    R70	0x46C350
    R69	0x450000
    R68	0x4403E8
    R67	0x430000
    R66	0x4201F4
    R65	0x410000
    R64	0x401388
    R63	0x3F0000
    R62	0x3E0022
    R61	0x3D00A8
    R60	0x3C03E8
    R59	0x3B0001
    R58	0x3A8001
    R57	0x390000
    R56	0x380000
    R55	0x370000
    R54	0x360000
    R53	0x350000
    R52	0x340820
    R51	0x330080
    R50	0x320000
    R49	0x314180
    R48	0x300300
    R47	0x2F0300
    R46	0x2E07FC
    R44	0x2C1F22
    R43	0x2B0000
    R42	0x2A0000
    R41	0x290000
    R40	0x280000
    R39	0x270001
    R38	0x260000
    R37	0x258204
    R36	0x240050
    R35	0x230004
    R34	0x220000
    R33	0x211E21
    R32	0x200393
    R31	0x1F43EC
    R30	0x1E318C
    R29	0x1D318C
    R28	0x1C0488
    R27	0x1B0002
    R26	0x1A0DB0
    R25	0x190624
    R24	0x18071A
    R23	0x17007C
    R22	0x160001
    R21	0x150401
    R19	0x1327B7
    R18	0x120064
    R17	0x1100FA
    R16	0x100080
    R15	0x0F064F
    R14	0x0E13F0
    R13	0x0D4000
    R12	0x0C5001
    R11	0x0B0018
    R10	0x0A10D8
    R9	0x090604
    R8	0x082000
    R7	0x0700B2
    R6	0x06C802
    R5	0x0500C8
    R4	0x041943
    R3	0x030642
    R2	0x020500
    R1	0x010808
    R0	0x00201C
    

    These are the register values on my device right after I set it to 4GHz, read directly from the LMX8410.

    I'm using the internal LO and also routing the VCO (or channel divider output) out through the LO port of the device.  I amplify the output, transmit it, and then route the received frequency back through the RF port to generate my baseband IQ values (which are displayed on the graph's Y axis in Volts).  I've set the internal termination of the LO port to High Z.  

  • Hi Raymond,

    Derek, the subject expert is OoO and will be back next week. Can you be wait for respond by him?

    Regards,
    Ajeet Pal

  • I played around with the data a bit more, it appears as though I am seeing a random 180 degree phase shift on the output data when using the DIV2 quadrature generator.  See below

    This is 10 different sweeps from 5500 to 6000MHz.  I lock the PLL, take 1024 samples, then increase the frequency and repeat the process.  Every 180 degree shift on the I data is accompanied by a 180 degree shift on the Q data (both have a sign change at the same time).  The output is clearly mirrored around a DC offset, but I still can't figure out what's causing the mirroring.  

    EDIT:

    It appears now that the 180 phase shift only occurs when I change VCOs.  I enabled VCO_CALSTART_CLOSE and the shifts are only occurring around VCO boundaries.  They are still random though.

  • Derek can respond once he is back.

    Regards,

    Ajeet Pal

  • Raymond,

    Are you ever synchronizing the internal synthesizer? I am wondering if the state of the DIV2 quadrature generator is effectively randomized by the VCO recalibration as it crosses the VCO boundary... it's been a few years since I drew the block diagram, but I believe I recall the SYNC feature can also reset the DIV2 quadrature generator, which should be able to eliminate any uncertainty in the LO phase even across VCO transitions.

    Regards,

    Derek Payne

  • I've implemented the SYNC function via the external pin but appear to be having the same issue.  I changed my MASH order to Integer to try out the Category 2 sync, but it didn't make a difference.  I'm pulsing the SYNC pin every time I change frequency, but the phase shift is still only occurring on the VCO boundaries which makes me think that the SYNC process isn't taking the DIV2 quadrature generator's output into account (or I'm not implementing SYNC properly, although I'm following the LMX2594 datasheet's directions and each pulse is triggering a VCO calibration).  

    On a possibly related note, I noticed that the N values in the TICS Pro software appear to be incorrect for this device when using the SYNC function.  The IncludeDivider factor is listed as 4, but I was unable to get a lock unless I used a divider of 2.  It seems as though the IncludeDivide factor already accounts for the DIV2 factor, so the software ends up factoring it in twice.  Maybe this is more evidence that the DIV2 Quadrature generator occurs separate from the SYNC?  

  • Raymond,

    There's some bits in the register map R80 (11, 10, and 9) that I don't think are mentioned anywhere helpful, but which seem important for LO SYNC functionality. Do you have these enabled? I didn't see them in your original settings. The procedure (if I understand correctly) should set SYNC_PIN_IGNORE to 0 and all other phase sync bits to 1; it seems SYNC_PHASE_MIXLO bit explicitly handles synchronizing the LO path.

    I'm also asking internally to see if we have any demonstrated method to SYNC the DIV2 element.

    Regards,

    Derek Payne

  • For the SYNC implementation I was setting R80 to 0x0E09 and the SYNC_PIN_IGNORE to 0, as well as enabling the SYNC_PHASE_PLL bit in R0.  I wasn't able to poll my OSCin signal so I couldn't ensure the setup/hold times in fractional mode, but I put the device into Integer mode and still had the same problem.  If I understood the datasheet correctly, there are no setup/hold timing restrictions on the SYNC toggle when I'm in integer mode.