DAC38RF82: DAC38RF82 I /Q phase error

Guangyan Liu

Part Number: DAC38RF82

Dear Expert ,

Good day !

Our customer use the DAC38RF82 to check the QPSK signal , sometime , the I /Q phase will have big deviation ,like the screenshot below

Normally , this value is 0.3 , but there is 10 percent will become 2.7 . the customer had test numerous chips , they had same problem , it seems like cause by the register setting ,

They set the dac38rf82 in 82121 mode , and 4x Interpolation , 6.4G sample rate , 1.6Ghz data rate , the FPGA use the xilinx XC7VX330T.

Could you provide any suggestions base on your experience how to solve it ?

BR,

Leon.liu

over 2 years ago

0 jim s over 2 years ago

TI__Guru* 91947 points

Leon,

Is the customer using the NCO? Are they using the DAC PLL or an external 6.4GHz clock? Please send the DAC register settings. Are they using the part in wideband-DUC mode (Table 9 of data sheet)?

Regards,

Jim

0 Guangyan Liu over 2 years ago in reply to jim s

TI__Intellectual 2130 points

Hi Jim，

Thank you for your help ,

The customer update the query below

DAC Problem.docx

BR,

Leon.liu

0 jim s over 2 years ago in reply to Guangyan Liu

TI__Guru* 91947 points

Guangyan,

The maximum SYSREF frequency can be per the JESD204B standard in this setup is 80MHz. SYSREF = data rate / (K * N) where N is a whole integer. Have them change the SYSREF frequency to either 80 MHZ or 80MHz / N.

Regards,

Jim

0 Guangyan Liu over 2 years ago in reply to jim s

TI__Intellectual 2130 points

Hi ,Jim

Sorry to reply you late , as these days are Mid-Autumn Festival in China.

Our customer feedback that , they had tried to change the SYSREF to 40M ,but the same problem is still exist ,

BR,

Leon.liu

0 jim s over 2 years ago in reply to Guangyan Liu

TI__Guru* 91947 points

Leon,

Have the customer make the following changes:

address = 0x5C data = 0x03 for pages 1 and 2

address = 0x24 data = 0x20 for pages 1 and 2

See attached file of DAC register settings I used that did not show this issue when configured per the customers settings.

Regards,

Jim

E2E_821_PLL_6.4_4x_200_ref.cfg

0 Guangyan Liu over 2 years ago in reply to jim s

TI__Intellectual 2130 points

Hi Jim

The customer had tried address = 0x5C data = 0x03 for Pages 1 and 2 and address = 0x24 data = 0x20 for Pages 1 and 2, but the IQ phase problem still occurred. Every time when reset JESD IP in FPGA, the phenomenon of excessive phase error is likely to occur. I think it may be related to sysREF. Is it caused by the dissynchronization in JESD chain building ?

But I did not found the root of the problem and how to solve it. please provide more suggestions

BR,

Leon.liu

0 jim s over 2 years ago in reply to Guangyan Liu

TI__Guru* 91947 points

Leon,

When issue occurs, is only the FPGA JESD IP reset or are they resetting the DAC as well? Are the clocks interrupted during this reset?

Can the customer try using an external 6.4GHz clock to see if the issue is possibly related to the DAC PLL?

Can they perform the NCO test in section 2 of the attached document to verify SYSREF timing is meeting setup and hold time with respect to the DAC clock?

Regards,

Jim

7723.Board trouble-shooting tips.docx

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DAC38RF82: DAC38RF82 I /Q phase error