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DAC38RF89: When debugging, 204B interface instability issue

Cherry Zhou
Mastermind 22235 points
Part Number: DAC38RF89

When debugging, everything works well when 204B interface channel rate is 10G. When at 12G, the SYNC signal is occasionally pulled low, causing resynchronization.

The other registers are unchanged, except for the corresponding modification to the two registers 0X3B,0X3C associated with the SERDES PLL. Then the customer has tried other channel rates, 8G is normal, but 11G is unstable. So the customer wonders it might be because of the high rate that caused instability.

The DAC is direct-picking and does not use up-conversion frequency and PLL. 

The 8G and 10G are good, so the basic configuration should be fine.

The customer would like to know what need to be aware when configuring.

Thanks a lot!

Best Regards,

Cherry Zhou

  • 0
    TI__Guru 66004 points

    Hello,

    The device is expected to support up to 12.5Gbps of Serdes rate over JESD204B interface.

    To double check if the Serdes PLL are configured correctly, please feel free to use the DAC38RF89 GUI to configure the end use case to cross check the register settings. The DAC38RF89 GUI can be downloaded from:

    https://www.ti.com/lit/zip/slac722

  • 0 in reply to Kang Hsia
    TI__Mastermind 22235 points

    Hi,

    Thanks for your reply!

    The latest updates as follows:

    The customer's configuration can work at every rate, but there is a problem with the Lrata rate > 10G, so the problem should be in the serdes-related register.

    Occasion 1: At Lrata rate of 12G, the Serdes PLL-related configuration is x"3b1801"; x"3c8051", DACLK is 2.4G, getting the clock is 2400/2/4 * 10 = 3G, and Serdes PLL output clock is 3G.

    Occasion 2: The other is x"3b0801", x"3c8029", getting the clock of 2400/2/2 * 5 = 3G.

    Both can work, but SYNC will occasionally go off.

    Mode: LMFSHd = 41121, dual DAC single LINK mode.

    The customer would like to know is there any familiar case which can help to solve the problem or could you please help to check this?

    Thanks a lot!

    Best Regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Mastermind 22235 points

    Hi,

    May I know is there any updates regarding the new questions?

    And here are some follow-up questions:

    The customer has changed the operating mode of the JESD204B interface, LMFSHd = 41380, but the data combined is 24bit and does not conform to the quad-byte processing of the 204B interface.

    And the customer has checked the manual but cannot figure it out, is there anything the customer missing?

    Thanks and expecting your reply!

    Best Regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Guru 66004 points

    Hi Cherry,

    The customer will need to read out the alarms upon the error to narrow down the root cause. This may be a signal integrity issue

    please see below ppt for recommendations on encountering the errors.

    1832.General Alarms for All Converters.pptx

    Cherry Zhou said:
    LMFSHd = 41380, but the data combined is 24bit and does not conform to the quad-byte processing of the 204B interface.

    This is a standard JESD204 F =3 mode. All FPGA IPs such as Xilinx and Intel JESD204 should be able to support this mode. If not, they may also refer to TI's JESD204 IP

    https://www.ti.com/tool/TI-JESD204-IP

    Could you please advise the end customer? This does not sound like a typical WI (wireless application). If it is a general catalog customer, I can forward this to HSC team for further review. Thanks. 

  • 0 in reply to Kang Hsia
    TI__Mastermind 22235 points

    Hi,

    Thanks for your reply!

    I have updated the answer to the customer, if there is follow-up questions I will update asap.

    Thanks a lot!

    Best Regards,

    Cherry