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DAC38RF89: PLL/VCO Jitter ＆VOUT Skew

user5163865
Genius 3325 points
Part Number: DAC38RF89

Hi,

Our customer have two questions.

1 Is there a spec for the output jitter of the internal PLL (including VCO)?
Also, is there a way to calculate jitter?

2. If we set the same data for two outputs and start sending,
Will there be a time lag (Tskew) in the output data between Vout1 and Vout2?
If it does occur, please let us know the specifications.
Also, the time lag (Tskew) is
・ Even if the power is turned off and on, if the settings are the same, is the time lag fixed?
・ If the settings are changed, will the time lag change?


It may be nonsense to ask for specs, but in that case it would be helpful if you could give me some advice.

Regards,

Hiroshi

  • +1
    TI__Guru 65954 points

    Hi Hiroshi-san,

    user5163865 said:
    1 Is there a spec for the output jitter of the internal PLL (including VCO)?
    Also, is there a way to calculate jitter?

    We have phase noise plot available for the DAC38RF89 datasheet. Please see figure 17 to figure 24. 

    Jitter is related to integrated noise over certain BW. Depending on customer's BW requirement, the jitter number may be calculated differently. I found one site that could calculate jitter from phase noise shapes

    https://rf-tools.com/jitter/

    user5163865 said:
    2. If we set the same data for two outputs and start sending,
    Will there be a time lag (Tskew) in the output data between Vout1 and Vout2?
    If it does occur, please let us know the specifications.
    Also, the time lag (Tskew) is
    ・ Even if the power is turned off and on, if the settings are the same, is the time lag fixed?
    ・ If the settings are changed, will the time lag change?

    By design, the two outputs within the same DAC38RF89 chip are deterministic and same latency. If the input through JESD204 to both DAC are the same, then the output will be aligned by design. This is also assuming the output has the same load and same 1.8V bias conditions.