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DAC38RF82: DAC38rf82 cannot establish jesd204b and meet the problem of elastic buffer match error

Part Number: DAC38RF82

Hello,There

    We are now debugging DAC38RF82, In the mode LMFSHD=42111 ,meet the problem of elastic buffer match error.The first non-/k/ doesn't match "match_ctrl" and "match_data" programmed values.

 Design details:

(1)LMFSHD=42111;

(2)FDac(DACCLK)=4800M,External Diff Clk;

(3).Single DAC(DAC A)

(4) 1 IQ pairs

(5) 4 serdes lanes

(6)Interprolation=6

(8)sysref=25MHz, lane rate = 8GHz

(9)FPGA  GTH refclk=200MHz

(11) K=16,RBD=15

the register setting sequence is:

let pin txenable be low 

let dac out of reset

0x000  0x8000

0x000  0x0000

0x000  0x7863

0x001  0x1000

0x002  0xFF00

0x003  0xFF00

0x10a  0x8310

0x10c  0x2402

0x10d  0x0000

0x10e  0x0000

0x10f  0xEFFF

0x110  0xFFFF

0x111  0xFFFF

0x117  0x0000

0x119  0x0000

0x124  0x0000

0x125  0x2300

0x127  0x1144

0x128  0x0000

0x14a  0x0F02

0x14b  0x0F00

0x14c  0x0F03

0x14d  0x0100

0x14e  0x0F6F

0x14f   0x1CC1

0x150  0x0000

0x151  0x00FF

0x152  0x00FF

0x153  0x0100

0x154  0x8DE0

0x15c  0x0000

0x15f   0x1203

0x160  0x7654

0x40a  0xF002

0x40b  0x0022

0x40c  0xA003

0x40d  0xF000

0x41b  0x0000

0x423  0xFFFF

0x424  0x1000

0x431  0x0200

0x434  0x0000

0x43b  0x2802

0x43c  0x8251

0x43d  0x0088

0x43e  0x8909

0x43f   0x0000

then start-up sequence:

0x124  0x0000

0x15c  0x0000

0x40a  0xF002

delay

0x40a  0x7002

0x000  0x7863

0x124  0x0020

dealy

0x15c  0x0003

delay

0x000  0x7860

delay

0x10d  0x0001

let pin txenable be high

QUESTION:

1. We read register  0x64 to 0x67; 

(1)random error of 0x800 will appear between 0x64 to 0x67

(2)we use alarm pin and it is always high,like the image,

2.we make the alarm pin enable,it will trouble proper dac work?

3.not mask alarms will bring any problems?

Best Regards,

Caps