DAC38RF83: Phase noise?

Hi Hiroshi-san,

We will need to take a look. Please advise if you can move the RF sampling rate up to higher sampling rate. I suspect this is due to the harmonic foldback. If you have higher sample rate, then the RF foldback will be less likely at 767MHz.

-Kang

Kang-san,

Sorry for the late reply.
Last week I gave your advice to our customer and I am waiting for a response.

Regards,
Hiroshi

Hiroshi-san,

Please also ask the customer to move the carrier by +/-1MHz to see how the noise shape is being moved. If it is move by 3x or 5x, then it may be 3rd order or 5th order harmonics. If it is moving 1:1 ratio, then it could be a clock mixing product. 

Kang-san,

Thank you for your advice.
I will report to the customer.

Hi Kang-san,

I understood the situation a little.

When the input signal of the DAC is a fixed value (DC)
Spurious is observed at the CW converted by NCO and the frequency 2.637MHz (= SYSREF frequency) away from the center frequency of the CW.

I think that this spurious can be seen in the part that looks like a step when the modulated signal is output.
The origin of spurious is unknown.

Due to hardware limitations, trying to change the sample rate is not easy and not possible.

We confirmed the NCO frequency dependence of the signal-to-spurious ratio.
The relationship was that doubling the NCO frequency reduced spurious emissions by 6 dB.

Additional confirmation,
1. Change the frequency of NCO
2. Change the frequency of the IQ input signal of the DAC
Either way, if the carrier is +/- 1MHz
The shape of the noise does not change.

Is it possible to investigate the cause of spurious and take countermeasures with this content?

Sorry for the difficult inquiry.

Best regards,
Hiroshi

Hi Hiroshi-san,

This is a multiplicative spur due to SYSREF coupling. When there are energy from the clock driver for the SYSREF signal, it gets modulated onto the CW or LTE signal. It is a 1:1 ratio movement and also a direct copy (Amplitude modulation) resulting double sided spur (i.e spurs at both Fout + SYSREF and FOUT - SYSREF).

We have seen cases like this and the advise is to have the customer turn off the SYSREF driver (tri-state). Please advise if the customer can tristate the SYSREF driver after the DAC38RF8x had been finished programming and initialization?

Kang-san,

I got the customer's evaluation result.

The clock to the DAC is supplied by LMK04821.

The spurious did not change when the SYSREF Driver (DCLKout3) to the DAC was powered down via LCPECL.
The spurious disappeared when the SYSREF Driver (DCLKout1) to the FPGA supplying the IQ signal was powered down via LVDS.

However, I don't think the customer system will work properly in this situation.
Should I understand that this is an unavoidable problem when using the SYSREF driver?

Best regards,
Hiroshi