Other Parts Discussed in Thread: , AFE7900, AFE7950
Is it possible to do a JES204B loopback on the digital level to verify the lanes's signal integrity?
I mean not converting to analog and sampling, but just looping the DAC bitstream onto the ADC bitstream.
One would expect the bitstream to be bit perfect if the lanes are properly designed.
We will also do an RF loopback to verify BER, and produce an eye diagram. But I would also like to verify that the JES204B lanes are properly designed and can carry the jes204b streams with zero errors.
At the moment I have a KCU105 eval board from Xilinx, and a AFE7444evm from TI. This is preperation work for when the PCB arrives with FPGA: KU11P, and AFE74444
Obviously such a loopback will work perfectly with these eval boards. So it "should" work exactly the same when we get our PCB back.
