Other Parts Discussed in Thread: LMK04828
We're testing AFE7444 and got phase jitter issue.
LMK04828 used to offer clock (360MHz) for AFE7444
AFE7444 internal PLL is activated and up-convert frequency to 5760MHz as DAC sampling rate.
As we loop back AFE7444 (RF loop back) on the single board, Phase Jitter is about +/- 0.2 degree.
As we use AFE7444 on 2 different baord: AFE7444 on board A as RF TX, while AFE7444 on board B as RF ＲX，Phase Jitter rapidly increased to+/- ４degree.
By tuning AFE7444 PLL_register (CP_ADJ Reg), Phase Jitter drop to +/- ３degree, but still far about our goal +/-0.2 degree
Question (1) Based on AFE7444 Loopback test result on single board, can we confirm the phase jitter is small due to ADC 's clock and DAC's Clock interaction?
So when AFE7444 got Tx/Rx loopback test under 2 different boards, the phase jitter will become worse as ADC 's Clock /DAC's Clock are non-correlated (even it's synchronized by LMK04828), right?
Question (2) Do we have solution to tune AFE7444 PLL Phase Jitter performance so phase jitter always as -/+0.2 degree, no matter under single board (RF loop back) test or different board test ?
