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Original question:

AFE7444: AFE7444

AFE7444: Why DAC reset required in AFE7444

ganesh singh1
Intellectual 400 points
Part Number: AFE7444

Hi ,

We are testing the AFE7444 with Ultrascale FPGA.

We noticed every time we change the Waveform we need to reset the DAC.

Can you know to tell us how can we fix it. or the reason behind it?

With regards,

Ganesh Singh

  • 0
    TI__Genius 10505 points

    Hi Ganesh,

    When you say 'reset the DAC', do you mean re-link JESD? 

    JESD link is independent of what data being transmitted. So changing the waveform being sent should not affect JESD link. 

    Is this on a custom AFE7444 board connected to an FPGA running your firmware? Are you using the TI JESD IP on FPGA?

    Regards,

    Vijay