Hi Team,
The shared international repeater project currently uses an AFE7769 (4T4R2FB) and an SN18064 (4T4R1FB). There are problems with the channel 3/4 of SN18064
- SN18064’s problems: it’s under the 4TR, dual sync mode (channel 1/2 transmits and receives 2 SYNCs; channel 3/4 transmits and receives 2 SYNCs). Channel 1/2 is normal. The SYNC of the transmitting channel of channel 3/4 can be pulled high, but there’s no signal output. The sync received by channel 3/4 is always low.
1) For the receiving channel of channel 3/4, the K code of lane3 cannot be seen in the FPGA data capture.
2) The FPGA sends the PRBS code and uses the algorithm in TI's K C function to check the errors of each lane. It is found that there are many errors in lane 3 listed as follows:
3) On the FPGA side, the GTY performs loopback, and the sync pin is looped back at the same time. The 4 lanes can send and receive smoothly, the data is normal, and the sync can be pulled high.
4) The jump wire outside FPGA loops back the GTY corresponding to lane3. Due to the jump wire, the speed cannot reach 10G and is reduced to 2.5G. On ibert, the prbs seems normal.
Therefore, I think that a problem has emerged when SN18064 is configuring lane3. Could you please help me locate where the problem occurs? Thank you in advance.
Best regards,
Katherine
