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DAC38RF82: SYSREF capture circuits & phase tolerance window

Part Number: DAC38RF82

My question is about Figure 31 in the section 8.3.10 SYSREF Capture circuits. I can understant how the SYSREF Statu Monitor record the phase information of the SYSREF event, and then the phase infromation is used to choose phase tolerance window. But I am quite confused why the phase tolerance can enjoy a large tolerance range ,llik R->R for phase window 00 (because I thought if SYSREF event locates at phi_3 region, there are possibility to violate the setup/hold window) . Besides, I cannot understand how the phase tolearance window 01 assign the alignment clock to "window 00/01 alignment edge".

BY the way, what's the function of register SYSREF_ALIGN_R and its field  ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT.

  • Hi Shuyuan,

    The SYSREF windowing tolerance (R→R, etc.) is simply referring to where SYSREF may appear in any given period of the device clock. This is why the "whiskers" are always 1 device clock period in width. You are correct about φ3 region, however this only applies if the transition is close to the device clock rising edge, R, and is accounted for within the device. In other words, the recorded phase will indicate the absolute best window region for the given device. I think maybe the figure (which is meant to ease this concept) is what is causing all of your confusion. Maybe the below drawing will help to clear this up.

    In the above image, if SYSREF (pink arrow) occurs near the device clock rising edge boundary (beyond what our device is capable of meeting timing for), the phase will be recorded as the next boundary which will guarantee timing constraints are satisfied (which would be the φ34  window). In this case, one would simply choose to operate in the φ34  window region as directed by the device phase recording. The LMFC and frame clock alignment would occur on the following device clock rising edge (approximately 1 device clock period later).

    The SYSREF_ALIGN_R register simply counts the number of times the device SYSREF block is in the R1/R3 state. These states are internal to the device and provide no useful information for our customers. As a result, this register can be ignored.

    Regards, Chase

  • Hi Chase, 

    Thanks a lot for your explanation. It is quite clear. 

    And I find another question about sysref capture circuit.  Field  SYSR_ALIGN_DLY is used to adjust the alignment event by +-1 device clock cycles. Is it achieved by software compensation (because I see the sentence " software compensation for phase misalignment due to PCB design errors" in the sysref capture circuits feature description at p39)? 

    Thanks

  • Hi Shuyuan,

    This is simply a field in the register map (SYSREF Capture Circuit Control Register , 0x24). The term "software compensation" is referring to the operation within the DAC38RF82 device itself which is performed to achieve this function of shifting SYSREF by ±1 device clock cycle.

    Thanks, Chase 

  • Hi Chase,

    I am still confused about how this shifting SYSREF 1 device clock cycle earlier is achieved.  It seems once you detect the upcoming SYSREF Signal , you already missed the -1 timestamp to generate LMFC signal. I have a guess that the period of SYSREF is recorded and then used to estimate the SYSREF rising edge, but i am not sure about it. If it doesn't work like this. how they achieve this.

    Thanks, Chase

  • Hi Shuyuan,

    I am not certain on the design of this feature. I would have to ask our design engineers for how this is done. If the SYSREF is considered as reference location and passes through a 1 clock cycle of latency device (such as DFF), it is simple to see how you achieve +1 clock cycle for LMFC output, etc. But to achieve the -1 clock cycle shift, I am not sure. The device might be architected with 2 DFFs on SYSREF and when selecting the -1 clock cycle setting, both of these devices are bypassed and the result is 1 less clock cycle. I suspect something like this is happening within the device, but I will ask. This may take up to a few weeks to hear back given the holiday season - many engineers are out from today through the beginning of next year.

    Regards, Chase