My question is about Figure 31 in the section 8.3.10 SYSREF Capture circuits. I can understant how the SYSREF Statu Monitor record the phase information of the SYSREF event, and then the phase infromation is used to choose phase tolerance window. But I am quite confused why the phase tolerance can enjoy a large tolerance range ,llik R->R for phase window 00 (because I thought if SYSREF event locates at phi_3 region, there are possibility to violate the setup/hold window) . Besides, I cannot understand how the phase tolearance window 01 assign the alignment clock to "window 00/01 alignment edge".
BY the way, what's the function of register SYSREF_ALIGN_R and its field ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT.