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AFE7950: AFE7950EVM + KCU105 bring-up. Read DDR to file error.

Part Number: AFE7950

Good day to all!

We are trying to work with AFE7950EVM and Xilinx KCU105.
We follow the steps of "AFE79xx EVM Bring-up" video, but when we click on the "Capture" button in HSDC software we get an error: "Read DDR to file. TIMED_OUT_ERROR".
There are no errors in Latte log.

State of the LEDs on the KCU105 board:
0 - OFF (Rx SYNC)
1 - ON (Tx SYNC)
2 - ON (Rx Reset done)
3 - Flashing (DRP CLK)
4 - Flashing (DXI CLK)
5 - Flashing (TX/RX CORECLK)
6 - Flashing (GT REFCLK)
7 - OFF (TX EMPTY)

We tried to change number of samples (HSDC capture option), Invert Sync Polarity and Invert Serdes Data, but the error still remains.
GTXCLK on AFE7950EVM board is correct, CLK_LAO is the same, 245.76 MHz. FMC VADJ is always 1.8 V. Eye diagrams on all lines are good. AFE7950EVM board power supply is 5V and current limit is 5A.
We use Latte v5.6 and HSDC v5.20.

What could be the problem?
There may be an error in the AFE settings in the INI file?

  • AFE79xx_2x2RX_24410_ini.txt
    [ADC]
    Interface name="KCU105_FIRMWARE"
    Number of channels=8
    Channel Pattern=1,2,3,4,5,6,7,8
    Data Postprocessing=1:32768
    \\operation:operand
    \\operaion
    \\0=bit shift
    \\1=xor
    \\2=and
    \\3=or
    \\4=not
    \\operand
    \\value(+ve if bitshift by right and -ve if bitshift by left)
    \\E.g 0:-2,1:1024
    \\bitshift by left 2 times and then xor by 1024
    Number of Bits=16
    Max sample Rate=500000000
    Register_Config="-"
    \\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
    DLL Version=1.0
    Read EVM Setup Procedure="EVM Setup Procedure not available"
    \\use <> as delimiter for newline
    [Version 1.0]
    JESD IP Core_CS=0
    JESD IP Core_F=4
    JESD IP Core_HD=0
    JESD IP Core_K=32
    JESD IP Core_L=4
    JESD IP Core_Lane_Enable=108
    JESD IP Core_M=8
    JESD IP Core_N=16
    JESD IP Core_NTotal=16
    JESD IP Core_S=1
    JESD IP Core_SCR=0
    JESD IP Core_Tailbits=0
    JESD IP Core_LaneSync=1
    JESD IP Core_Subclass=1
    JESD IP Core_JESDV=1
    \\MIF Config= 0.611G to 12.5G:RX:RX_PMA_x40
    Config JESD Rate = 0.611G to 1.5G:x10, 1.5G to 12.5G:x40
    \\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
    \\These MIF Files need to be present under MIF Files Folder
    \\Fabric PLL Counter = 0.611G to 12.5G:0x080202
    Invert Sync Polarity = 0 
    \\Invert Sync polarity, 1:invert; 0: do not invert
    \\Invert Serdes Data, 1:invert; 0: do not invert
    Enable Individual Lane Inversion = 1
    Invert Serdes Data = 255 
    \\Invert Serdes Data = 0 
    Transceiver Mode = 1
    \\1:xcvr mode; 0: TX/RX only mode
    Lane Mapping=lane0:5,lane1:6,lane2:3,lane3:2
    Bit Packing = 0
    \\0 - Data are not bit packet.
    \\1 - Data are bit packet (MSB aligned) without any padded zeros
    \\skipreconfig=0
    
    \\Mixer Type =1
    \\0-> Straight Mixer - Default - (Fout=Fin+NCO)
    \\1-> Down Mixer (Fout=Fin-NCO)

  • Hi Evgenly,

    Our team will work on testing this in our lab and get back to you with an answer next week.

    One thing that may also be helpful to you in the mean time is that in the AFE79xx secure folder we have example reference designs for the AFE79xxEVM + KCU105 using the TI204c IP. 


    Regards,

    David Chaparro

  • Hi Evgeniy,

    After checking on our side it was found that the AFE79xxEVM + KCU105 using the KCU105_FIRMWARE in HSDC Pro is not supported. This firmware was created by a 3rd party company who no longer supports firmware.

    For support on the AFE79xxEVM + KCU105 we have moved over to using the TI204c IP for firmware. We have a reference design available in the AFE79xx secure folder that can be used. 

    Access to the TI-JESD204c IP can be request from this page: https://www.ti.com/tool/TI-JESD204-IP 

    Regards,

    David Chaparro