• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 10 subscribers
  • Views 188 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE7900: need help to choose the appropriate configuration

Florian Jutisz
Prodigy 30 points
Part Number: AFE7900
Other Parts Discussed in Thread: AFE7901, ,

Hello,

I am currently architecturing a new system based on an AFE7901 and a Xilinx Zynq UltraScale+.

Our need is to record then playback RF signals with a bandwidth of 140 MHz, that are received with a central frequency between 100 MHz and 5100 MHz.

The expected FPGA baseband input/output are I & Q samples, coded on 16 bits each, at a rate of 200 MHz.

What would be the AFE7901 recommended configuration ? 

My understanding is that RF signals are directly sampled. AFE7901 can sample at up to 3 GSPS. Is this sufficient for RF signals at 5 GBPS ?

I also have the impression that only I samples are transmitted. How can I get both I & Q samples ?

Taking all this in consideration, what would be the LMFS configuration of the JESD link ? Shall I use JESD204B or JESD204C ?

Thanks & Regards,

Florian.

  • 0
    Prodigy 30 points

    I mention both AFE7900 and AFE7901. Actually the final target is AFE7901, but we plan to start our development with AFE7900 evaluation board.

  • 0 in reply to Florian Jutisz
    TI__Genius 10655 points

    Hi Florian,

    For 140MHz signal bandwidth, you can use data rate of 187.5MSPS complex. Usable bandwidth is about 80% of complex data rate which is ~150MHz at 187.5MSPS complex data rate. 

    When running ADC at 3GSPS, decimation factor of 16 can be used to get 187.5MSPS output data rate.

    JESD mode I suggest for this data rate is LMFSHd: 28810. Using 64b/66b encoding, lane rate would be 12.375Gbps. This is supported by Xilinx Zynq UltraScale+ FPGAs.

    The JESD204 frame format for 28810 mode is as shown below. As you can see both I and Q channel data is sent on JESD204 interface. 

    Though the maximum ADC sample rate of AFE79xx is 3GSPS, it can directly sample input signal from 100MHz to 5100MHz by undersampling. Note that signal band of interest cannot cross Nyquist boundaries. 

    Generally, when using AFE790x, ADC input is limited to one Nyquist zone in one use-case due to anti-aliasing filter at front-end. 

    AFE7900EVM should be used to evaluate all AFE790x family parts. AFE7900 supports all modes supported by AFE790x family parts.

    Regards,

    Vijay