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AFE7906: Design Queries Reg

Deva Guru
Prodigy 225 points
Part Number: AFE7906
Other Parts Discussed in Thread: AFE7900EVM

Hi,

I am designing a custom board using AFE7906 and have the below query,

1) Since AFE7906 has only RX and no TX, is SYNCB-OUT connection to FPGA required?

2) What is the purpose of JTAG pins and how should i connect ? can i perform Boundary scan using on board FPGA or external device?

3) In DC135A_AFE7900EVM, 27uF feed-through capacitor is used to isolate multiple rails ( VOUT_1p8V_CLK and VDDA_GPIO_1p8 ). How to calculate the Rejection offered by the feed-through? Is it better to use a ferrite instead of this to increase PSRR/Isolation?

4) In DC135A_AFE7900EVM, VDDA1P8 and VDD1P8GPIO are shorted together. can i power this using a Buck convertor or an LDO is mandatory?

Awaiting your reply at the earliest.

Thanks in-advance,

Deva

  • 0
    TI__Mastermind 18001 points

    Hi Deva,

    1. When using the AFE7906 the SYNCB-OUT signal is not required and can be left unconnected or used as a general GPIO pin.
    2. The JTAG can only be used to perform boundary scan. When not being used JTAG Test Reset must be pulled low. 
      1. Please note that BIST0 and BIST1 should be set appropriately. Described in the Pin Functions table. 
        1. BIST0 should be set high for normal operation.
        2. BIST1 should be set low for normal operation.
    3. These components are actually a ferrite/cap filter. The equivalent circuit is ferrite bead -> shunt cap -> ferrite bead. This specific component is inherently designed to have a notch filter around 2Mhz and provide a rejection of about 15 to 25 dB. 
      1. The following two links can be used for additional information.
        1. https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/794567/dac38rf82evm-ferrite-beads-vs-three-terminal-capacitors 
        2. https://www.ti.com/lit/an/slyt720/slyt720.pdf 
    4. The 1.8V rails are the most sensitive and we recommend that a LDO be used. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 225 points

    Hi David,

    Thanks for your quick response.

    For performing Boundary scan, where should the JTAG pins of AFE be connected to? Either to FPGA IO pins (or) to some 1x6 header similar to Xilinx, if so what external debugger is required?

    Also is it possible to Daisy chain the JTAG of 2Nos of AFE's?

    Thanks in-advance,

    Deva

  • 0 in reply to Deva Guru
    TI__Mastermind 18001 points

    Hi Deva,

    The JTAG pin connection should be made based on your system design. They should be connected to your programmer/deubgger that is performing the boundary scan. If this is off board then you can use a 1x6 header similar to Xilinx, otherwise you can connect it directly to the programmer/debugger. 

    Yes, it is possible to daisy chang the JTAG of multiple AFE's. To do this please follow the standard procedure for daisy chaining multiple chips with JTAG. 

    Regards,

    David Chaparro