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AFE8000EVM: AFE8000

Haim Bachar
Prodigy 45 points
Part Number: AFE8000EVM
Other Parts Discussed in Thread: AFE8000

Hi Guys,

We have VCK190 connected to EVM AFE8000 set up.

We are tring to activate JESD204C interface and we saw that sys_clk (375Mhz) is missing, it should come from the EVM AFE8000 via R317, but this resistor is not assembled .

any idea , why is that so ?

Where does the Versal FPGA should get the refrence clock (not the sysref) for the JESD interface ?

Thanks

Haim

Thanks

Haim

  • 0
    TI__Genius 14761 points

    Hi Haim,

    This looks to be an issue with our BOM/Schematic. These two resistors should not be DNI'd by default. When using the TI204C-IP reference designs a clock is expected from those pins. Please install these two resistors on your EVM and you should then be able to get the 375MHz clock at the FPGA. 

    We will work on updating this for future boards.

    Regards,

    David Chaparro