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AFE7950: Simultaneous Tx Rx with TSW14J58EVM and AFE7950

ram krips
Prodigy 40 points
Part Number: AFE7950
Other Parts Discussed in Thread: TSW14J58EVM

Tool/software:

Hi David,

Due to the long delays in the reply, we have shifted activity to a different project and will get back to Simultaneous Tx Rx with TSW14J58EVM and AFE7950 next month.

As the current available commands do not suffice for our request we didn't document the trials.

We do hope by the time we will get back to tests with these boards, TI FW will be capable of performing at least as was with previous HW versions.

If the ability is better (as with previous HW) it is even better.

I am copying my request from the last communication:

I am using TSW14J58EVM with AFE7950 and would like to record 2Rx channels while transmitting 1Tx channel.
It seems that synchronized operation isn't possible so I would like to find out whether a less demanding setup is possible:


1. The Rx and Tx needn't be synchronized (nevertheless, they should overlap most of the time).
2. SW init ("trigger") - NO need for external HW trigger at this stage.
3. Tx and Rx would be memory based (I generate the Tx signal and analyze the Rx signals in python).

4. Max Bandwidth

Please provide sample code for the init and execution

Best Regards,

Ram

  • 0
    TI__Expert 5045 points

    Hi Ram,

    We are looking at this request with our team internally. Please give us some time to look over this and get back to you with a response.

    For now, could you share the information in the table below about your specific mode of interest?

    TX

     

    # of TX enabled

    ?

    Fs DAC [GSPS]

    ?

    Single or Dual Band

    ?

    Interpolation

    ?

    FB

     

    # of FB enabled

    ?

    Fs ADC[GSPS]

    ?

    Single or Dual Band

    ?

    Decimation

    ?

    RX

     

    # of RX enabled

    ?

    Fs ADC[GSPS]

    ?

    Single or Dual Band

    ?

    Decimation

    ?

    JESD

     

    Encoding (If not sure we can pick for you)

    ?

    Available Lanes on FPGA

    ?

    Max Lane Rate Supported by FPGA [Gbps]

    ?

    Clocking

     

    Use AFE internal PLL

    ?

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 40 points
    Hi Camilo,
    Most of the replies are included in my previous message.
    I will first repeat the most important:
    #Tx = 1
    #Rx at least 2
    instantaneous TxRx (see above for comment if not possible)
    Fs for Rx and Tx : Preferably maximal (instantaneous bandwidth of at least 500MHz, preferably more)
    Other parameters:
    Single/dual band: as simple (fast) as possible.
    no interpolation required
    Clocking internal: for simplicity 
    Please select all other parameters to obtain best performance.
    no need for fb
    I'll be glad if you could produce a simple sample that transmits some random noise in a single Tx channel and records it in two Rx channels (all use the same carrier).
    If any other simplification is required to move things forward please contact me by mail or phone.
    Best,
    Ram
  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 40 points

    Hi Camilo,

    Is there an expected schedule for a solution ?

    Best,

    Ram

  • 0 in reply to ram krips
    TI__Expert 5045 points

    Hi Ram,

    We have reached out to you through email in regards to this.

    I will close the post so that we can continue the conversation through there.

    Best,

    Camilo