Tool/software:
Dear Team,
We got the access for TI204C-IP (JESD204B/C rapid design IP) and its example design files from TI, and we are creating the example design for Zynq UltraScale+ device (ZCU102 EVK board).
While Building the example design in Vivado tool We have observed some error prints and critical warning ,attaching the below image for reference.
Please guide me if I am missing anything or doing something incorrectly. Your assistance is appreciated.