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Original question:

AFE7769-3P5EVM: user guide to interface AFE7769D-35EVM with TSW14J58EVM

AFE7769-3P5EVM: I am observing the below error find the screen shot attached

Kalyan Giri
Prodigy 20 points
Part Number: AFE7769-3P5EVM


Tool/software:

The errors I am getting are

1) AFE configuration in progress.

2) Could not detect FPGA Reset FTDI, Please reset FPGA manually.

Thanks and Regards,

Kalyan Giri

  • 0
    TI__Expert 3295 points

    Hi Kalyan,
    You can ignore that error and continue. with the next steps in the quick start guide.

    Please let me know if you face any issues in next steps.

    Regards,
    Bhavesh Atul Rathod.

  • 0 in reply to Bhavesh Rathod
    Prodigy 20 points

    Hi Bhavesh,

           Ok, we continued with the next step in the quick start quide. In the GUI we are able to observe the spectrum as per the waveform we loaded. but when are measuring in the MXA we are not able see the spectrum. Only a tone is visible.

     

    Fullscreen TI.error.txt Download 
    VI_ERROR_LIBRARY_NFOUND: A code library required by VISA could not be located or loaded.
Missing VISA Libraries: Only Dummy Instruments will be created. 
Please install VISA Libraries for connecting to instruments.
Installation Information:
Keysight VISA Libraries: Keysight IO Libraries Suite 2024, Release Date: 25-March-2024, Build No.: 18.4.30319.0 .
Keysight IO Libraries Suite 2024 can be found in "Previous Versions" section from below link or by visting the Keysight website directly.
https://www.keysight.com/in/en/lib/software-detail/computer-software/io-libraries-suite-downloads-2175637.html
AFE77xxDLibraryPG1p0
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Misc-B RegProgrammer - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
FPGA Reset device not found
Reset the FPGA and try again.
FPGA Reset device not found
Refreshed GUI
Power Card - USB Instrument created.
#================ ERRORS:5, WARNINGS:1 ================#
#================ ERRORS:0, WARNINGS:0 ================#
Refreshed GUI
Device Initialization for ChipVersion: 1.0
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 9830.4
laneRateRx1: 9830.4
laneRateFb: 9830.4
laneRateTx0: 9830.4
laneRateTx1: 9830.4
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 9830.4
laneRateRx1: 9830.4
laneRateFb: 9830.4
laneRateTx0: 9830.4
laneRateTx1: 9830.4
DONOT_OPEN_Afe77xxDPG1p0_FULL - Device registers reset.
chipType: 0xa
chipId: 0x77d
chipVersion: 0x10
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK Configured.
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE Reset Done.
pll1: True; LO Frequency: 2949.12
FPGA Reset device not found
FPGA Reset device not found
FPGA Configured.
AFE MCU Wake up done.
pll0: True; LO Frequency: 3500.0
pll1: True; LO Frequency: 2949.12
pll2: True; LO Frequency: 1900.0
AFE all PLLs configured.
AFE SerDes configured.
AFE Digital Chains configured.
AFE PAP configured.
AFE DAC Analog Writes configured.
AFE RX Analog Writes configured.
AFE FB Analog Writes configured.
AFE JESD configured.
AFE GPIO configured.
AFE TX IQMC-LOL Correction configuration Complete
AFE DPD Block configuration
AFE DPD Block configuration Complete
AFE RX IQMC configuration Complete
AFE RX AGC configuration Complete
AFE CFR configuration Complete
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
AFE Configuration Complete
#================ ERRORS:7, WARNINGS:0 ================#
#Error: name 'resync' is not defined
# "", line 1, in 
# NameError: name 'resync' is not defined
# 
# 
#================ ERRORS:1, WARNINGS:0 ================#
#Error: name 'resync' is not defined
# "", line 1, in 
# NameError: name 'resync' is not defined
# 
# 
#================ ERRORS:1, WARNINGS:0 ================#
Signal Info:
____ RMS power (dBFs): -8.222
____ Peak power (dBFs): -0.202
____ PAR (dB): 8.02
____ DC Value (dBFs): -66.305
____ Frequency: -25.0 - 25.0 : -11.149
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
Signal Info:
____ RMS power (dBFs): -15.008
____ Peak power (dBFs): -4.008
____ PAR (dB): 11.0
____ DC Value (dBFs): -73.477
____ Frequency: -25.0 - 25.0 : -15.008
Setting RBD to: 2.0
Sent Custom Signal

############################
setOverrideTdd(0, 1367)
TDD Set.

############################
setRxDsaAttn(0, 15, 0)
Set RX DSA
setFbDsa(0, 3, 0)
Set FB DSA
setTxDsaAttn(0, 15, 48)
Set TX DSA

############################
setRxDsaAttn(0, 15, 0)
Set RX DSA
setFbDsa(0, 3, 0)
Set FB DSA
setTxDsaAttn(0, 1, 0)
setTxDsaAttn(0, 14, 48)
Set TX DSA

############################
setOverrideTdd(0, 1367)
TDD Set.
Signal Info:
____ RMS power (dBFs): -8.227
____ Peak power (dBFs): -0.202
____ PAR (dB): 8.025
____ DC Value (dBFs): -59.241
____ Frequency: -25.0 - 25.0 : -8.227
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
Setting RBD to: 2.0
Sent Custom Signal
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
Signal Info:
____ RMS power (dBFs): -15.008
____ Peak power (dBFs): -4.008
____ PAR (dB): 11.0
____ DC Value (dBFs): -73.477
____ Frequency: -25.0 - 25.0 : -15.008
Setting RBD to: 2.0
Sent 5G Signal
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
Setting RBD to: 2.0
Sent 5G Signal
Signal Info:
____ RMS power (dBFs): -16.299
____ Peak power (dBFs): -3.803
____ PAR (dB): 12.496
____ DC Value (dBFs): -79.682
____ Frequency: -25.0 - 25.0 : -16.299
Signal Info:
____ RMS power (dBFs): -8.223
____ Peak power (dBFs): -0.203
____ PAR (dB): 8.02
____ DC Value (dBFs): -138.222
____ Frequency: -25.0 - 25.0 : -11.234
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 0 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
lane0 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
lane1 Errors=0b10000000000000; Got errors: Serdes loss of signal(LOS) indicator; 
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0
###################################
Setting RBD to: 2.0
Sent Custom Signal

############################
setOverrideTdd(0, 1367)
TDD Set.

    Thanks and Regards,

    Kalyan Giri

  • 0 in reply to Kalyan Giri
    TI__Expert 3295 points

    Hi Kalyan,
    I see that the FPGA is not connected to Latte. Can you please connect with me on the forum I can share more details and debug steps there as this is a public post.

    In the meantime you can try the following:
    1. Close the latte
    2. Power cycle FPGA and EVM
    3. Start Latte (make sure you see AEF EVM card detected)
    4. Proceed with steps in quick start guide. (The latest version of Latte SW is 1.6 I am assuming you are using latest version)


    Regards,
    Bhavesh Atul Rathod.