AFE7900EVM: JESD204B Sync Problem

Ekin Özer

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900

Tool/software:

Hello,

We are working on establishing communication between our JESD204B design, developed on our FPGA, and the AFE7900 EVM. Our current situation is as follows:

The FPGA RX line successfully completes the CGS and ILA states and deasserts the SYNC signal after the CGS state. We are also able to see data coming from the AFE side.
However, when we observe the FPGA TX line, we see that it remains stuck in the CGS state. The expected SYNC signal from the AFE side is not being deasserted. Furthermore, when programming the AFE through the Latte GUI, we encounter the following errors:

########### Device DAC JESD-RX 0 Link Status ###########
CS State TX0: 0b10101010 — Expected: 0b10101010
FS State TX0: 0b00000000 — Expected: 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0x0

###################################

########### Device DAC JESD-RX 1 Link Status ###########
CS State TX0: 0b10101010 — Expected: 0b10101010
FS State TX0: 0b00000000 — Expected: 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0x0

###################################

No additional alarms or errors are reported by the Latte program. We have also manually checked the related registers and confirmed that no other errors are present.

To better understand the problem, we removed the AFE79 board and connected a loopback card instead. In this test, our FPGA design successfully synchronized with the loopback card, and we were able to observe the same data pattern on both the TX and RX lines.

Therefore, our main question is: why is the JESD204B RX interface of the AFE7900 EVM unable to synchronize with the FPGA TX synchronization pattern?

After confirming that the loopback card was working properly, we attempted the same test using the SERDES loopback function of the AFE7900 EVM. Instead of observing a continuous data flow on the TX and RX lines as expected, we found that both lines showed no data activity and remained stuck at a constant value.

While researching online, we came across a discussion with TI (link ) that seems quite similar to the issue we are experiencing. However, since the conversation eventually continued via email, we could not access the full details. This is why we are reaching out to you directly.

We would greatly appreciate your advice on the following points:

- How can we identify JESD204-related errors on the AFE79?
- Which registers can be used to gather more information regarding these errors and to control the SYNC output?
- In the Latte interface error log provided above, what exactly do the “CS state” and “FS state” represent? We checked the register list but could not find a definition, only the required values. Do you have any insights or suggestions regarding this?
- Is it necessary to complete the CGS and ILA states in order to use the SERDES loopback properly? In other words, is the SYNC signal required on both the RX and TX sides?

Any information you could share would be extremely valuable to us. Thank you in advance for your time and support.

Regards,

3 months ago

0 David Chaparro 3 months ago

TI__Mastermind 18351 points

Hi Ekin,

For interpreting the JESD errors you can refer to the app note linked below. In regard to your question on "CS" and "FS" state, CS and FS state registers show the current state of JESD204 frame alignment. If CS state is as expected, receiver has locked to K28.5 characters. FS state would go to expected value when initial lane alignment sequence is done and transmitter switches to sending data. If FS state is stuck to 0, transmitter may not have switched from sending K28.5.

The issue you are seeing is likely related to the SYNC signal, can you confirm that the "sysParams.syncLoopBack" parameter is set to 'True' in your Latte script. Also, are the SYNC signals set up for LVDS or CMSO Sync and is the FPGA set up to match this? If you can share your Latte script we can also take a look at these.

https://www.ti.com/lit/an/sbaa637/sbaa637.pdf

Regards,

David Chaparro

0 Ekin Özer 3 months ago in reply to David Chaparro

Prodigy 20 points

Hi David,
Thank you for the quick response.

I am using the Latte script provided in one of the example designs, TI_IP_10Gbps_8Lane_ConfigLmk.py. After configuring the system with this script, I also doubled the DDC factor in the GUI to reduce the lane rate from 9.8304 Gbps to 4.9152 Gbps. You can see the script code in the attachments. The parameter "sysParams.syncLoopBack" appears to be set to True.

Fullscreen TI_IP_10Gbps_8Lane_ConfigLmk.txt Download

'''
Validation :  AFE79xx Library Version 
				v1.67, v1.74
Case			RX					TX						   FB						CLK					Notes
----	-----------------	  -----------------			-----------------			-----------			------------
1		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in interleaved mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
		
2		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in straight mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
'''
setupParams.skipFpga 				= 1
sysParams							=	AFE.systemParams
setupParams.fpgaRefClk 				= 122.88#184.32#
AFE.systemStatus.loadTrims			= 1

sysParams.fbEnable 					= [False]*2
sysParams.externalClockTx			= False
sysParams.externalClockRx			= False
sysParams.FRef                    	= 491.52
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 2949.12*4

sysParams.enableDacInterleavedMode	= False 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx                	= ["44210","44210","44210","44210"]	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["22210","22210"]
sysParams.LMFSHdTx                	= ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity		= [False]*8
sysParams.jesdRxLaneMux				= [0,1,2,3,4,5,6,7]	#[0,1,2,3,4,5,7,6]
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity	= [False]*8
sysParams.jesdRxRbd					= [4, 4]

sysParams.rxJesdTxScr				= [True]*4
sysParams.fbJesdTxScr				= [True]*2
sysParams.jesdRxScr					= [True]*4

sysParams.rxJesdTxK					= [32]*4
sysParams.fbJesdTxK					= [32]*2
sysParams.jesdRxK					= [32]*4

sysParams.ncoFreqMode 				= "1KHz"
	
sysParams.txNco0					= 	[[5400,1800],		#Band0, Band1 for TxA for NCO0
										[500,1800],        #Band0, Band1 for TxB for NCO0
										[2500,1800],        #Band0, Band1 for TxC for NCO0
										[1800,1800]]        #Band0, Band1 for TxD for NCO0

sysParams.rxNco0					= 	[[5400,1800],		#Band0, Band1 for RxA for NCO0
										[500,1800],        #Band0, Band1 for RxB for NCO0
										[2500,1800],        #Band0, Band1 for RxC for NCO0
										[1800,1800]]        #Band0, Band1 for RxD for NCO0

sysParams.fbNco0					= 	[1800,1800]			#FBA, FBC for NCO0
sysParams.fbNco1					= 	[1800,1800]			#FBA, FBC for NCO1
sysParams.fbNco2					= 	[1800,1800]			#FBA, FBC for NCO2
sysParams.fbNco3					= 	[1800,1800]			#FBA, FBC for NCO3

sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

sysParams.ddcFactorRx             	= [6]*4			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [6]*4
sysParams.ducFactorTx             	= [24]*4


## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	2949.12/1024
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x00
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1
lmk.rawWriteLogEn					= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 0
sysParams.jesdCDLvdsSync			= 0
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'DAC_SYNC0',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'ADC_SYNC1',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
setupParams.skipLmk	=	False

AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()

In regard to SYNC signal, I did not check the LVDS option. Sync signals are expected to be LVCMOS18 from the FPGA side.

There is also another thing I would like to ask. In somewhere along the debug guideline it mentions that this problem might be caused by incorrect polarity in some of the lanes. In the schematic of the AFE EVM, the JESD lanes (DP0–7) are not mapped directly to the receiver lanes (SRX1–8); both the lane numbering and signal polarity differ while the mapping on the FPGA side is direct both in lane numbers and the polarities.So according to this, I changed the Lane Polarities from the GUI after running the script file. Can you also check the below screenshots to confirm the lane polarities?

In addition, for now all LMK clock outputs, except for SYSREF, are configured to 122.88 MHz.
Is it possible to change some of the LMK clock outputs directly through Latte? On our own AFE board, we are able to configure the LMK via SPI to generate not only the REFCLK output but also different other clock outputs with different frequencies using the TICS Pro tool. However, I am not sure if the same can be done in Latte. Could you provide any information on this topic?

Again, thank you for your support.

Best regards,
Ekin.

0 Ekin Özer 3 months ago in reply to David Chaparro

Prodigy 20 points

Hi, I just wanted to kindly check if you had a chance to look into this thread. Any updates or suggestions would be greatly appreciated.

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AFE7900EVM: JESD204B Sync Problem