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TPS43060: TPS43060: RF noise affecting 868 MHz antenna

Sergii Zavgorodnii
Prodigy 35 points

Part Number: TPS43060

Hello TI Team,

I am troubleshooting a radiated-noise problem on a board using the TPS43060RTER as a 15 V → 24 V boost converter (up to 2 A).

image.png

The system includes an 868 MHz RF transceiver, and the boost converter generates strong interference that significantly degrades antenna performance. Even with no load, the converter produces strong broadband noise, and applying load does not change the EMI level much.

Using a near-field probe, the highest emission peak is around 120 MHz 

image.png

The strongest field is detected around the boost inductor area.
The original inductor was TMPC1265HP-100MG-D, and I also tested a shielded inductor (SRR1280-100M), but this did not noticeably reduce the interference.

On the low-side MOSFET gate (AOD66406), the waveform shows a strong negative dip exactly at turn-on.

image.png

 This dip is much deeper than what I observe on the official TPS43060EVM-199

image.png
This looks like excessive ringing or gate-source bounce, which could be generating high-frequency radiation and may correlate with the 120 MHz peak.

What I have tried:

Adding a 10 Ohm gate resistor → slightly reduces ringing, but the negative dip remains.

image.png

Adding an SW-node snubber (R = 1 Ohm, C = 100 pF) → no significant improvement.

Because the 120 MHz EMI peak matches the ringing frequency seen on the oscilloscope, I suspect the gate waveform might be the primary source of radiation.

My questions:

1.Is such a downward “kick” on the MOSFET gate during turn-on normal for TPS43060, or does it indicate parasitic inductance/coupling or layout issues?

2.Could this gate-node behavior realistically be the main cause of the strong 868 MHz interference?

3.Any recommendations for suppressing this effect - gate-resistor tuning, additional snubber, or checking components?

Thank you!

  • 0
    TI__Intellectual 2010 points

    Hello Sergii,
    thank you for using E2E.
    We will check and get back to you by latest end of week.
    Best Regards,
    Johannes

  • 0 in reply to Johannes Braun
    TI__Mastermind 34240 points

    Hello Sergii,

    Thanks for the detailed problem description.

    I agree with you that the gate signal ringing is the most likely root cause for the poor EMI behavior.
    Regarding your questions:

    1. This level of downward kick is abnormally high in your design. Especially when the signal goes back down below the enable threshold of the MOSFET, it could lead to a second, unintended switching of the FET.
    Parasitic coupling and layout issues can be a root cause for this.

    2. Yes.

    3. My first recommendations would be to reduce the ringing with gate resistors and snubber, which you already tried.
    The gate resistor seems to already provide some small improvements.
    Regarding the snubber, you can consider adjusting the values to match the resonating frequency. We have a snubber calculator tool within our Power Stage designer:
    https://www.ti.com/tool/POWERSTAGE-DESIGNER
    Within the schematic, I noticed the BST capacitor is larger than necessary with 1uF (C75). We generally recommend to dimension the BST cap at least one decade smaller than the VCC cap (4.7uF) to avoid potential VCC drops. Hence, 100nF should already be sufficient.
    However, this might be unrelated to the main problem at hand.

    Would you be willing to share your layout files, especially the structure of both HDRV and LDRV gate driver paths and according return paths via GND and SW?

    Thanks and best regards,
    Niklas

  • 0 in reply to Niklas Schwarz
    Prodigy 35 points

    Hello Niklas,

    Thank you for your quick reply and helpful recommendations.

    As requested, I have attached the layout files, for your review.

    TI_TPS43060_v3.zip

    Best regards,

    Sergii

  • 0 in reply to Sergii Zavgorodnii
    TI__Mastermind 34240 points

    Hi Sergii,

    Thanks for the fast reply.
    There are two major points I found when going through the layout files:

    - The gate driver traces and according return paths are close to each other, which is good, but the path goes directly below the magnetic field of the inductor.
    This comes with the risk that parasitic effects of the inductor are coupled into the gate driver lines.

    - The footprints on the VSYS, GND and +24V polygons all use thermal relief pads. This makes it easier for soldering, but much worse in regard to noise.
    On the switch node plane (NETC65_2), there are solid pads with no interruptions, which is good. I would recommend to do the same for all other components that are part of the power stage. Especially the MOSFETs, ceramic caps and snubbers.

     

    The component placement of inductor, MOSFETs and IC looks okay to me.

    Best regards,
    Niklas