• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 10 subscribers
  • Views 455 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TRF3765 Selecting PLL Divider Values

Eduard Hasenleithner
Prodigy 20 points
Other Parts Discussed in Thread: TRF3765

I'm reading the documentation of the trf3765 and am struggling with an ambigous statement therein. On page 35 I read "Then, calculate the maximum frequency to be
input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by Equation 6."

The sentence as written might imply that one should select the prescaler in such a way that fN,Max does not exceed 375 MHz. But this contradicts that the prescaler has already been selected by Equation 5. Furthermore, the PLL_DIV_SEL calculation will always lead to an fPM requiring the 8/9 prescaler, rendering the 4/5 prescaler useless.

 Can somebody make some clarifying statements on this issue?

  • 0
    TI__Expert 3300 points

    The prescaler value is selected by equation 5.

    P will either be 4 or 8. Therefore, the prescaler will either alternate between dividing by 4 then dividing by 5 or it will alternate dividing by 8 and 9.

    You need to know the maximum frequency feeding in to the digital divider, fN. If the prescaler is set to 4/5, then the worst case is fVCO/4. Some of the time, the prescaler will be dividing fVCO by 4 and feeding it into the digital divider. If the prescaler is set to 8/9, then the worst case is fVCO/8. This value may not exceed 375MHz.