• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 9 subscribers
  • Views 915 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

GC5016 DDC PFIR issue

Andres Espin
Prodigy 130 points


Hello

I'm using two GC5016, one in 4 channels DDC mode and the other in 4 channels DUC mode. The parameters of my design are:

CK: 40MHz

Ftune: 10MHz

cic_dec: 64

fir_dec: 2

fir_int: 2

cic_int: 64

Everything is ok except the following: I'm using the gc5016_filterdesign MATLAB script to design DDC and DUC FIR filter taps. First of all, I use a delta for the DDC filter and design the filter for the DUC, and everything works as expected. When I design the filter taps for the DDC and load them into the GC5016 I found that, without input signal, there are three tones at 10MHz, 10.104MHz and 9.896MHz. I'm reviewing all the documentation and posts on this forum, but I can't find neither explanation or idea wich explains what is happening.

Please can you help me to solve this? I'm completely stopped at this point

Thanks in advance

Andres

  • 0
    TI__Mastermind 37500 points

    Hello,

    The GC5016 DDC and DUC used with the context of the TSW4100, has components for tuning, decimation, interpolation, PFIR filter design, and the IO pin control for the DDC output and DUC input. 

    If you have a project that has changed the decimation and interpolation ratio OR splitIQ vs 4 channel mode OR the number of PFIR taps, then the IO timing has to be checked.  If there is an FPGA to receive the DDC output, register the data, and then have the DUC pick up the FPGA output, and perform the up conversion, then the Frame strobe signals are not as important.  If you are using the TSW4100 design, you must match the Frame strobe using the sync delays as outlined in the user guide.

    You want the DDC Frame Strobe to be output aligned with the DUC Frame strobe, in some cases +/- 1 clock. 

    The filter design between the DUC and DDC can be quite different.  The TSW4100 software in some modes is reducing the number of PFIR taps, to reduce the repeater latency, this changes the Frame Strobe IO timing, so it has to be matched again.

    The other thing that can cause multiple tones, other than IO timing, is resyncing the NCO at the wrong time.  If you are changing the NCO tuning word, once the tuning update is complete, the freq_sync, nco_sync needs to be set to OFF again.

    If the DUC input IQ is not the proper sequence, you can get time displaced I and Q which cause multiple signals to be seen at the DUC output.

    In a diagnostic sense, there is a DC 1/2 scale constant that can be applied at the DDC input, you then set the DDC NCO for an INBAND tone, (ie 50khz), at the DDC channel output, you should have a 50Khz complex tone.   You note the DUC NCO IF, and add the 50Khz, this is the expected output.  You set the sumchain in the DUC to only look at the first test channel.  You adjust the Frame Strobe delays using an oscilloscope to align the falling pulse edge.  You now look at the DUC output you should have the single tone at IF + 50Khz.  To check the system response you can change the DDC test NCO to sweep the DUC channel. 

    Regards,

    Radio Joe

     

     

     

     

  • 0 in reply to Radio-Joe
    Prodigy 130 points

    Thanks Joe, It's and I/O timing problem. I'm waiting for a new board which solves this issue in our project. I'll send feedback about the results.

    Another question I've got is the following: I'm trying to change PFIR taps directly from my host processor, once the initial configuration of the GC5016 is done. What I'm doing is to create an initial configuration with two filters, through cmd5016. Then I generate a .h file and add it to my processor project. In my code I have a routine which reads the cofficients of the filter from .h file (on page addresses 0x0 to 0xf, 0x20 to 0x2f,...) and writes'em back to the desired channel. This method works more or less, but there are two problems:

    1. The output signal power is modified when I change the filter (the signal is always in the middle of the pass band)

    2. Some times the output signal spectrum is completely modified when I change the filter.

    I suppose that I have to change other parameters rather than filter taps (fir shift?, fixed gain?) and load all together to the GC5016 syncing in some way. I was searching but I couldn't find a procedure to do this. Please can you send me that?

    Thanks again

    Regards

  • 0 in reply to Andres Espin
    TI__Mastermind 37500 points

    Hello

    The PFIR reloading is not a normal programming condition for the GC5016.  There are special requirements.

        a) the PFIR and CIC decimation / interpolation ratios must not change

        b) the number of PFIR taps, even/odd/no symmetry must be the same

        c) tbe DDC or DUC output, will not be stable during the coefficient update

        d) although there are provisions for switching banks of coefficients, this is not done automatically by the cmd5016 program, it requires hand calculation

             of the coefficient addresses, and some of the PFIR state machine registers, so this is not described

        e) during the PFIR filter design, scaling the sum of the taps to the same value, between the two filters, will make the PFIR gain similar.

        Program the GC5016 from the initial h file

        Generate the 2nd GC5016 .h file where the PFIR taps are different, possibly the Baseband Gain are different

        write 0xFF00 to address 0

        write the register differences

        perform the remainder of the init sequence   

    Regards,

    Radio Joe

        

     

  • 0 in reply to Radio-Joe
    Prodigy 130 points

    Thanks Joe,

    My application agrees with all the special requirements you wrote, but I have a question about point d: I'm going to use several filters, all of them with 255 taps, so I cannot use switching banks. Must I have to recalculate coefficient addresses in this case?

    Regards,

    Andrés

  • 0 in reply to Andres Espin
    TI__Mastermind 37500 points

    Hello,

    If you use the same number of coefficients, the same PFIR decimation, and the same symmetry the location of the coefficients will be the same.  If there is only one standard filter at a time, the default GC5016 programming will setup the coefficient base address, and offset address.

    If the sum of the coefficients are the scaled to a power of 2 so the PFIR_shift is the same value, for all filters. 

    Note: in the last email, when you want to change the PFIR coefficients, there will be a disturbance in the DDC output.  Once the DDC is stable, you will either need to resync the DUC, or manage the DDC -> BB -> DUC to restore the proper sync DDC writes to BB interface, then DUC reads from BB interface.

    Regards,

    Radio Joe

     

     

  • 0 in reply to Radio-Joe
    Prodigy 130 points

    Hello Joe, thanks again for your support, it was very useful to me.