How much noise figure is added by TSW4100 kit?
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The TSW4100 does not have a noise figure. There is degradation of the signal, so we could discuss an effective SNR.
In the input processing we have the IF Filter, ADC Transformer, Common Mode Bias, ADC, and its clocking. This ADC sampling has an effective SNR based on the IF sampling frequency, Effective Number of Bits in the ADC, and clock quality. The ADS5545 ENOB is 12bits. The TSW4100 uses 160Msps as the sample clock, the IF selected is 120Mhz, 2nd Nyquist zone. The clock solution quality, and ADC clock filter, must meet the requirements to utilize the 12bit ENOB. A 12bit ENOB can be simply translated to a 12x6 72db SNR . There are other ADC metrics for SFDR, SINAD also.
The Digital Down Converter (DDC) will tune, filter, and decimate. In this example if we have an input BW of 80Mhz, and an output decimate by 4, 80% filter, we will lower the output noise, in affect filtering the 160/4 * .8 so the passband of each channel is 32Mhz. Over the transition band to the stopband of each filter, we would attenuate the noise over 40Mhz to the stopband of the digital filter; we would attenuate over the transition frequency for 4Mhz around each side of the passband. We would pass 32Mhz (in this example). The GC5016 out of band attenuation for the DDC is at least 80db. Most of the digital filtering in the repeater is to filter out the unwanted energy.
The baseband processing of the 16bit data from the DDC and to the DUC would have an SNR floor of at least 90db.
The GC5016 Digital Up Converter (DUC) provides interpolation, filtering, tuning each channel, and summing. Each of the Downconverted channels (1 to 4) are gain adjusted, filtered, and interpolated. The filtering suppresses the interpolation images to at least 80db. The input gain, and sum chain gain scale the added channels for the digital output.
The DAC5688 provides interpolation, sinx/x correction, and bulk mixing to the IF frequency. The DAC conversion quality also depends on the clock quality, and if the clock solution provides both the high frequency clock (ie no DAC PLL is used). The DAC does have intermodulation and SNR products. The AC performance characteristics of the DAC for the 120Mhz IF are better than 65db SNR. In our example, we could use a DAC clock of 4, and interpolation of 4, for a 640Mhz DAC operating clock. The DAC interpolation, clocking, Tuning all contribute to the DAC performance.
The limiting SNR in the above example is at the DAC interface, of about 65db. This can be improved with different output frequency plans, so the ADC and DAC have equal SNR contributions.