I'm trying to use the CD74HC4046A PLL w/VCO chip to set up a low-frequency PLL circuit. I'm observing odd behavior and am having a hard time understanding what is going on with the chip. I am using phase comparator #1 because I want the chip to default to f0 rather than some other frequency:
The values of R1 and C1 are set to yield a default f0 of about 320 Hz. When I power on the chip (with no external signal coming in) I observe a fairly stable square wave from the VCO at approximately the desired frequency. If I test by setting an external function generator to the output frequency of the VCO, when I connect that input signal to the chip it does not lock, and the output frequency of the VCO moves to another value (higher by ~ 13 Hz for a breadboard version of the circuit with DIP type chip, and lower by ~ 50 Hz for a PCB version with SOIC type chip). If I then adjust the function generator output frequency to this "suggested" value, it locks, although the lock indicator (pin 1) does not generally pull high. It can stay locked over a range of about +/- 2 Hz.
R1 is about 650k Ohms for the breadboard version and about 900k Ohms for the PCB version. C1 is about 20 nF in both cases. R2 is not installed. I see the same behavior with a simple passive RC filter and an active version of that filter. The feedback loop has a ~ 20k Ohm resistor and a 100 nF capacitor. The function generator is set for an output amplitude of about 2.75 to 3.0 V p-p.
According to some notes on using the chip this setup ought to work pretty well...only it doesn't.
Can anyone help?
I need the chip to be able to lock at f0, at a minimum.