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TSW38J84EVM: SerDes lanes Query

Part Number: TSW38J84EVM

Hi, I have a question relating to the SerDes lanes on the TSW38J84EVM board. Within the user manual under the basic test setup it says "On the Quick Start tab, setup the controls as shown in Figure 8. For the dual-channel DAC3XJ82 choose "2" for the number of SerDes lanes. This configures the TSW3XJ8X EVM to use clocks generated onboard by the LMK04828 and 122.88 MHz VCXO. The DAC will be programmed for 1 lane per DAC, 4x interpolation, and an input data rate of 368.64 MSPS."

If I were to set the SerDes lanes to 1 would both of the DACs share the same Lane?

I am only trying to do the most basic tests I can to show functionallity.

Thanks