While designing a board for the AFE7070, I came across multiple issues:
- Does the LVDS_P/_N output, if unused, need to be terminated?
- If LVDS output isn't used at all, does LVDSVDD18 need to be
- connected to 1.8 V?
- decoupled separately?
- The maximum currents
- I_IOVDD,
- I_CLKVDD18,
- I_DACVDD18,
- I_LVDSVDD18 and
- I_DACVDD33
are inconveniently unspecified in the datasheet table on p.5.
Can a maximum supply current for these be clarified?
This is kind of central to power supply design in low-power mass application.
- In Dual Input Clock Mode, it seems that DACCLK_P and CLK_IO can be identical, in which case the data lines should be changed and finished changing in the negative period of DACCLK_P=CLK_IO. Is that correct?
- Optional: Does the RFOUT pin withstand operation without load (i.e. with an impedance mismatch -> infinity)?
- Optimally: Is there a mode which allows an RF signal path test during manufacturing, and if so, how to access it and what LO/clock would have to be supplied?
Thank you in advance,
Marcus Müller