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ADC32RF80: Zero IF conversion for 720MHZ QPSK input with the bandwidth of 320 MHz

Part Number: ADC32RF80
Other Parts Discussed in Thread: ADC32RF82, ADC10D1500

Hi, We are planning to develope a QPSK demodulator for 720 MHZ RF input signal with band width of 320 MHz. For it, Im working for the suitable Zero IF ICs and ADCs. So, whether can I use the ADC32RF80 IC for this purpose. If so, what will be the input settings (like RF, NCO, clock) and outputs? Pl suggest for the suitable hardware  selection.

  • Hi,

    ADC32RF80 is a RF sampling ADC. Therefore you can set the NCO same as the carrier frequency. Given your carrier frequency, you can set the sampling clock to 2457.6MHz which gives you another potential candidate - ADC32RF82. You can use our EVM design which includes clocking and power management circuitry for reference. This reference design may also be helpful: https://www.ti.com/lit/ug/tiduc85/tiduc85.pdf?ts=1588180763214

    Regards,

    satish.

     

  • How the ADC32RF82 with fractional sampling frequency can perform the zero IF conversion? Can  you brief the details of generation of NCO frequency please.

  • The NCO frequency is generated internally in the ADC with 16-bit resolution and the down-conversion is in digital domain.

    if your question on NCO frequency generation is general in nature, please refer to articles on DDS. We can't share the specifics of our design as it's considered proprietary.

  • We are planning to develop a COSTAS loop type implementation for QPSK Demodulation. The QPSK input is cenetred at 720 MHZ with the bandwidth of 320 Mbps. I have attached the realization plan (1st diagram) using the IC ADC32RF82. But to use this IC with sampling frequency of 2457.6 MHz as you said, I have following doubts. Can you Please clarify.

    (1)    The 16 bit word for NCO frequency initial generation and later in subsequent stage, the phase/ frequency offset correction word can it be generated using FPGA ? If so, how to link that to NCO of ADC32RF82?

    (2)    For 720 MHz is single NCO recommended?

    (3)    I want to enable internal DDC. Then is single DDC sufficient? How to finalize the configuration?

    (4)    From the ADC32RF82 data sheet, I have been observed DA[0,1] and DA[2,3] outputs. Are they quadrature shifted outputs ? Can you explain the relation in timing diagram?

    (5)  If the outputs are quadrature signals , then can I use them as Mixers outputs in the COSTAS loop , as shown in 2nd diagram of attachment?Hardware Realization_KUD.docx

  • 1. With the choice of FS=2457.6M and given the 16-bit resolution for NCO generation, the NCO can be set exactly to 720MHz, same as the carrier frequency in your case. The ADC output will then be at 0IF. I'm not sure what you meant by linking the FPGA to NCO in the ADC. There's no support of external feed for NCO. However, the sysref signal (in JESD204B subclass 1) can be used to reset the NCO phase in the ADC. You can align if you can do the same inside FPGA. 

    2. In your case single NCO will be enough. Dual NCO is used when you have more than one band and want to TDD between them.

    3. Yes, single DDC looks enough. The following mode should meet your requirements:

      

      # of lanes will determine the SerDes rate.

    4, 5. The digitized output is down-converted digitally to give quadrature outputs, same as the digital outputs of a traditional 0IF architecture.

  • Thank you very much for your support. With reference to your comments, with single NCO, I can get the zero IF I data. But as I shown in my block diagram, I need Q output simultaneously and at 90 degree shift of  NCO . Seems simultaneous is possible if I choose two NCOs. Please correct if I'm wrong.

    How to maintain the 90 phase shift please suggest. Do you have any sample designs for this application ?

    Can I get demo of the evaluation board for this frequency requirements? If so please provide the details.

    Link to NCO from FPGA means NCO  word generation in FPGA and sending to this chip. I understood it is not possible as NCO is internal to the chip. So this point is clarified. Thank you.

  • Also, w.r.t  your explanation if I choose the normal ADC10D1500 , with a sampling frequency of 720 MHz, can I get the zero IF samples? Then what is the benefits of ADC32RF82 otherthan higher sampling ranges?

  • You don't need 2 NCOs for IQ outputs. The complex down-conversion in digital is per NCO and gives quadrature outputs as shown in the figure below. NCO generation and the quadrature down-conversion is handled in the device internally.   

    Yes, trying it on our evaluation board is a good idea. Please contact your local TI sales person to procure one.  

  • My understanding is that your signal BW is 320MHz centered around 720MHz. You'll have to down convert it before digitizing with an ADC sampled at 720MHz, to prevent issues from folding and spectrum inversion. With the ADC32RF82, you don't have to go through the down-conversion. You can digitize it first and then down-convert, all done internally by the ADC. That's the advantage of using the ADC32RFxx. You'll need an anti-aliasing filter.