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LM15851: RF sampling output bandwidth question

Josh Wilson1
Prodigy 30 points
Part Number: LM15851

Hello,

I am looking at using the LM15851 in an RF receiver application. The data-sheet states that the part is capable of an output bandwidth of 1GHz with 4X decimation. I am wondering if that means that my RF real input bandwidth can be 1GHz (slightly less to protect against aliasing) but in practice can i really get away with having a 1GHz real RF bandwidth with a 4GSPS sample rate and 4X decimation. I guess what i am really asking is that i would think 4GSPS/4X decimation factor =1GSPS sample rate and therefore i would have a real RF input bandwidth max of 500MHz. I understand that this part is taking IQ samples so is that where I am missing the connection between the sample rate and real bandwidth? 

  • 0
    TI__Guru* 91947 points

    Josh,

    The data rate will be 1Gsps but this data consists of both I and Q data. If you were to process the FFT, you would use a complex FFT to show both negative and positive frequencies. This bandwidth would then be -500MHz to +500MHz. See figure 3-5 in the attached ADC12J400EVM User's Guide for an example of this.

    Regards,

    Jim

    User's Guide.pdf

  • 0 in reply to jim s
    Prodigy 30 points

    Is the data rate out of each of the I and Q outputs at 1Gsps? So we are effectively streaming 2Gsps of IQ data to the FPGA on separate 1Gsps I and Q channels? 

  • 0 in reply to Josh Wilson1
    TI__Guru* 91947 points

    The ADC output data rate is 1Gsps. I and Q data are interleaved so they are coming out at 500Msps each.

  • 0 in reply to jim s
    Prodigy 30 points

    Thanks Jim, I am still a bit confused. I thought since we are taking IQ samples that we are effectively getting twice as many samples, and hence twice the bandwidth vs. real sampling. So for this example since we are sampling at 1Gsps we would only have 500MHz of real bandwidth if this was a real sample ADC, the data rate into the FPGA would be 1Gsps. Since this ADC is sampling with IQ data, while we are still sampling at 1Gsps the data rate into the FPGA would be 2Gsps (twice as many samples) and our effective bandwidth is doubled to 1GHz. Can you help me understand what I am messing up with this? 

  • 0 in reply to Josh Wilson1
    TI__Guru* 91947 points

    Josh,

    My mistake. Both I and Q data will be coming out at 1Gsps after going through the JESD conversion. It will be two separate data busses. They will not be running at 2Gsps.This will provide twice the data over a real data case.

    Regards,

    Jim