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AFE7769: JESD questions

Part Number: AFE7769

Hi, 

we're trying to understand and config the AFE7769 JESD, there're several questions come up when we bring up our own 7769+ZynQ board.

please kindly help to answer

1)  The expected ADC-JESD TX  LMFSHd is ''28810", however the generated script divides it as 2x"14810" to each JESD core.

      Does this mean 2 links and FPGA should set up 2 independent links for it?

2)  Please give explanation how to use register 54 to config sync-in MUX.   an example is appreciated.

3)  Please give explanation on sync-out MUX(reg 55)  and sync-combiner (reg 61)

4)  What's de default polarity of JEST TX RX? should we change anything if there's no inversion on PCB and FPGA side?

5)  Is there register to indicate sync_in status and ILAS status?

6)  If we want to change lane mapping, we just need to re-config the LaneMux register.  anything else?  

Thank for your support in advance.