I have a AFE7799 EVM board. I connect this board to Xilinx ZCU 111 board via FMC connector. I set FMC voltage to 1.8v
I made a block design for Zynq MPSoC FPGA using Vivado and Xilinx Jesd204 ip to get data from AFE77xx EVM. ( I only connect 4 receiver lanes) The design is similar to example design(KCU 105 AFE example) given by Texas Instruments.
The core and sysref clocks to my FPGA design are supplied through LMK clock chip on EVM via FMC connector.
I configure EVM using LATTE and basic_bring_up_case 1.py script. (Rx configuration is 2 link 24410). I only change scrambling configuration. To see the signal clearly and easily debug the lines, I switch off the scrambling option.
When I configure the EVM and Xilinx board the sync signal goes high and no problem is seen in the code group synchronization.
The problem is when apply a sinusoidal signal to Rx1 input of the transceiver(3.51 GHz) and try to observe the digitized data from the axi stream output of the jesd ip I could not observe a perfect sinus shape but a noisy signal. The envelope of the signal is sinus like is but very noisy. I expect a 10Mhz sinus signal)
When I try to debug jesd ip I realized that unexpected K chars are coming aperiodically in the data phase after code group and ILAS phase. It seems that there is a frame alignment problem.
I inspect eye digrams using Xilinx IBERT tool seem that eyes are wide open.
Could you suggest any reason for unexpected K chars?
Do you have any Zynq MPSoc example design other than KCU105 design( KCU105 design is outdated and uses old config tools)