Hello TI Team,
We are trying to bring the AFE7422 using SPI. Please share the Register call back information of DAC and ADC reset buttons.
Thanks,
Preethika S
Hi Preethika,
The image you attached is not viewable. To reset AFE7422 before starting SPI programming, RESETB pin can be used. See below snippet from Programmer's guide for details.
Regards,
Vijay
Hi Preethika,
To get the register log of any function in GUI, select "Seq. Dump Mode" to "ON for PG3.0" as shown in below image.
Register writes get logged in "logFile.txt" located at "C:\Users\Public\Documents\Texas Instruments\AFE74xx\Log Files"
PFA log files for DAC and ADC buttons highlighted in the image you sent.
-- ************************************************************************ --
-- [Note]
-- This configuration script is auto-generated by AFE76xx GUI Python Script.
-- SW Version : 1.85 RC4
-- Date : 2021-02-02 14:49
-- ************************************************************************ --
-- Sequence of SysRef_Continuous_Mode_Set() --
SPIWRITE 0x139 0x2 --Sysref Pulse
SPIWRITE 0x139 0x3 --Sysref Continuous
-- End : Sequence of SysRef_Continuous_Mode_Set() --
-- Sequence of Tx_Jesd_Resync() --
-- Sequence of Tx_DAC_Encoder_INIT_CLK_SYNC_En() --
Page List to be opened: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x3
SPIWRITE 0x2c 0x0 --By default, disable FRCLOCK DIVIDER and ENCODERCLK_SYNC
Page List to be closed: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x0
-- Step 1: Start SYSREF pulses Start the JESD204B RX Init Block
Page List to be opened: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x3
SPIWRITE 0x21 0x7
-- Clock SYNC enable to SYSREF and clock divider enable >> Hence, SYSREF should be enabled at this moment
-- >>> Is this still true for PG3.0?
-- >>> Enable only for DAC path to be used
SPIWRITE 0x2c 0xc3 --DAC encoder initialization/clock sync enable (Using SYSREF) [0] + full rate clock_divider enabled [1]. For PG2 and PG3, FRCLK needs to be enabled.
SPIWRITE 0x20 0x3 --Set JESD204B RX Init-state = HIGH
Page List to be closed: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x0
-- End : Sequence of Tx_DAC_Encoder_INIT_CLK_SYNC_En() --
-- Sequence of Tx_DAC_Encoder_Pulse_Register_Blk_Cnfg() --
Page List to be opened: ['TX_TOP0_TX_DUC0P0', 'TX_TOP0_TX_DUC1P0', 'TX_TOP1_TX_DUC0P0', 'TX_TOP1_TX_DUC1P0']
SPIWRITE 0x10 0x55
-- [DAC clock generation]
-- 0x4D actually controls the whole clock generation for DAC path including Encoder clock and clocks for interpolation paths.
-- Hence, this register should be set to non-zero value during the very initial path configuration.
SPIWRITE 0x4d 0x0 -- DUC Clock Divider don't use SYSREF pulse (reset pulse register circuit)
SPIWRITE 0x4d 0x2 -- DUC Clock Divider use only the next sysref pulse and resynced ... means clk is restarted.
SPIWRITE 0x80 0x0 -- DUC JESD RX don't use SYSREF pulse (reset pulse register circuit)
SPIWRITE 0x80 0x6 -- DUC JESD RX uskip one pulse and then use next
Page List to be closed: ['TX_TOP0_TX_DUC0P0', 'TX_TOP0_TX_DUC1P0', 'TX_TOP1_TX_DUC0P0', 'TX_TOP1_TX_DUC1P0']
SPIWRITE 0x10 0x0
-- End : Sequence of Tx_DAC_Encoder_Pulse_Register_Blk_Cnfg() --
-- Sequence of Tx_DAC_Encoder_INIT_CLK_SYNC_Off() --
SPIWRITE 0x11 0x0
Page List to be opened: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x3
SPIWRITE 0x2c 0xc2 -- turn on encoder clk sync ena, but turn off the ENCODERCLK_SYNC_EN
SPIWRITE 0x20 0x0 -- Set JESD204B RX Init-state = HIGH
Page List to be closed: ['TX_TOP0_TX_DIGP0', 'TX_TOP1_TX_DIGP0']
SPIWRITE 0x11 0x0
-- End : Sequence of Tx_DAC_Encoder_INIT_CLK_SYNC_Off() --
-- End : Sequence of Tx_Jesd_Resync() --
-- Sequence of SysRef_Pulse_Mode_Set() --
SPIWRITE 0x139 0x3 --Sysref Continuous
SPIWRITE 0x139 0x2 --Sysref Pulse
-- End : Sequence of SysRef_Pulse_Mode_Set() ---- ************************************************************************ --
-- [Note]
-- This configuration script is auto-generated by AFE76xx GUI Python Script.
-- SW Version : 1.85 RC4
-- Date : 2021-02-02 14:50
-- ************************************************************************ --
-- Sequence of SysRef_Continuous_Mode_Set() --
SPIWRITE 0x139 0x2 --Sysref Pulse
SPIWRITE 0x139 0x3 --Sysref Continuous
-- End : Sequence of SysRef_Continuous_Mode_Set() --
-- Sequence of UnGate_SYSREF_TO_RXBLK() --
-- Sequence of UnGate_SYSREF_MUX_TO_RXBLK() --
Page List to be opened: ['TRAFFICCNTRL_0']
SPIWRITE 0x11 0x8
--Set Mux to ungate SYSREF for ADC Block
SPIWRITE 0x1a0 0xb8
Page List to be closed: ['TRAFFICCNTRL_0']
SPIWRITE 0x11 0x0
-- End : Sequence of UnGate_SYSREF_MUX_TO_RXBLK() --
Page List to be opened: ['jesd_Houdini_AB', 'jesd_Houdini_CD']
SPIWRITE 0x17 0x8
SPIWRITE 0x17 0xc
SPIWRITE 0x17 0xc
SPIWRITE 0x45 0x0
SPIWRITE 0x45 0xe0
SPIWRITE 0x45 0x0
Page List to be closed: ['jesd_Houdini_AB', 'jesd_Houdini_CD']
SPIWRITE 0x17 0x0
-- End : Sequence of UnGate_SYSREF_TO_RXBLK() --
### DELAY() - Note that this step requires WAIT for 1000[us]
-- Sequence of Gate_SYSREF_TO_RXBLK() --
Page List to be opened: ['TRAFFICCNTRL_0']
SPIWRITE 0x11 0x8
SPIWRITE 0x1a0 0xfc
Page List to be closed: ['TRAFFICCNTRL_0']
SPIWRITE 0x11 0x0
-- End : Sequence of Gate_SYSREF_TO_RXBLK() --
-- Sequence of SysRef_Pulse_Mode_Set() --
SPIWRITE 0x139 0x3 --Sysref Continuous
SPIWRITE 0x139 0x2 --Sysref Pulse
-- End : Sequence of SysRef_Pulse_Mode_Set() --Regards,
Vijay