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TSW40RF80EVM: TSW40RF80EVM LOAD DEFAULT ADC32RF45 SYSREF

Part Number: TSW40RF80EVM
Other Parts Discussed in Thread: ADC32RF45

TSW40RF8x EVM GUI LOAD DEFAULT
The setting of SYREF of ADC32RF45,
Is SDCLKout_PD of CLKout 4 and 5 of the LMX0428-Clock Outputs tag turned ON,
and is the SYREF output to ADC32RF45 set to unused?

  • Hi,

    If I understand your question correctly, you are asking the reason that the SYSREF output to the ADC is set to powered down after the initial starting up. There should be SYSREF running during the ADC + FPGA initialization of the JESD204 link. However, we recommend to turn off the SYSREF to avoid coupling of the SYSREF signal to the RF signal. If there are sysref coupling, you will see two SYSREF tones modulating onto the RF spectrum