• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 9 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TSW40RF80EVM: TSW40RF80EVM ADC32RF80 SYNC pin

user1120926
Prodigy 110 points
Part Number: TSW40RF80EVM
Other Parts Discussed in Thread: ADC32RF45

Connect the analog board TSW40RF80 to the FPGA board TSW14J57.
The FPGA board has a JESD IP that receives the ADC32RF45 analog board.

It synchronizes only when the config data is downloaded to the FPGA board.
Even if I press the RESET button on the FPGA board and reset the JESD IP, it does not resynchronize.

! The ADC Sync pin setting is the default inversion mode.

After synchronization, use the analog board control software TSW40RF8xEVMGUI.
ADC32RFXX-ADC32RFXX-ADC Configuration tag
ALTEA's Quartus app resynchronizes when Invert SYNC  is turned OFF and ON (v).
Monitored with the Signal Tap Logic Analyzer tool.

Even if the SYNC signal of the FPGA board changes from Low (synchronous state) to Hi (asynchronous state), it does not resynchronize.
I monitored the LVDS signal of the SYNC PIN of ADC32RF45 with an oscilloscope and confirmed that it was Hi (asynchronous state) and Low (synchronous state).

It seems that the SYNC pin on the ADC32RF45 is not working.
Is there a condition to put Hi (asynchronous state) of SYNC signal?

  • 0
    TI__Guru 66014 points

    Hi,

    The JESD204 IP synchronization occurs on the JESD204 RX IP side. In this case, it is the FPGA. The ADC will output K28.5 upon SYNC request = low, and output data during SYNC request = hi. You should be able to see the transition in your signal tap logic analyzer. 

    Your FPGA should have indication on what's passing or what's not passing.

    By default when using HSDC PRO with the TSW40RF8x, the HSDC PRO "capture" button initiates the sync request for ADC to output K28.5. it sounds like you are using your own JESD204 IP, and you will need to configure the correct IP error code on the FPGA side for further debug. 

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 110 points

    >By default when using HSDC PRO with the TSW40RF8x, the HSDC PRO "capture" button initiates the sync request for ADC to output K28.5.

    Could you please tell me the register settings and procedure for sync request for ADC?

  • 0 in reply to user1120926
    TI__Guru 66014 points

    Hi,

    The sync request is coming from the FPGA. This depends on your RTL code. The ADC only accepts the sync request, not initiating the sync request.