This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF80: Output power gain is Non-Linearity

Guru 17960 points
Part Number: DAC38RF80

Attached test results for Input to Output Gain look like non-linearity.

Please let me know about the reason of non-linearity.

I assumed that output gain is constant, because not using input Gain adjustment.

But below test results are change the output gain.

I want to know these results depend on DAC38RF80 spec or external problem.

※Orange: 10dB, Blue: 5dB, Light blue: 0dB, Green: -5dB

Please see test condition below;

・Signal generator (SG) output CW: 3.96GHz

・DAC38RF80 receive signal from FPGA, and confirmed DAC output signal on spectrum analyzer (SA).

・On above condition, DAC output gain measured on the condition of input level and DAC GAIN changing.

 (DAC GAIN are set 10dB, 5dB, 0dB, and -5dB)

Best regards,

Satoshi

  • Hello,

    There was a separate thread to our direct email. We have inquired the following:

    Please provide guidance on the ADC being used. You mentioned that output power level looks non-linear and depends on the input level. Where is the input level being referred?

     

    Is it from the SG -> RF circuit -> ADC -> FPGA -> DAC?

    Or is it only FPGA -> DAC (without data from ADC).

     

    Please advise. Eben can then take a look at this problem.

  • Hi Kang

    Thank you for reply,

    I looking forward answer by Eben or Kang.

    Input revel is referred on  SG -> RF circuit area.

    When SG -> RF circuit area set -20dBm level, FPGA's digital area become -35dBFS.  

    Please let me know if you need additional information or condition.

    Best regards,

    Satoshi

  • Hi Satoshi,

    Please ask the customer to decouple the ADC in the linearity testing. Please ask the customer to send out signal only from the FPGA to the DAC. Check the performance again when FPGA send signal (i.e. single tone, two tone, etc) and match the datasheet condition. This step is needed to ensure the DAC is compliant to the datasheet performance. Right now you are getting combinations of SG, RF circuits, ADCs and other signal chain linearity performance. 

  • Hi Kang

    I apologize my reply delay,

    FPGA single tone was not have, instead of customer information below,

    ・I update gain graph for RF to DAC output below. (Vertical axis is gain: dB, horizontal axis is input level: dBm)

    ・Next, below is the relation for RF to DAC input side (= FPGA output side), RF input is changing and DAC gain is fixed -5dB.

     I looked like linearly specification.

      (Vertical axis is DAC input gain: dBFS, horizontal axis is input level: dBm)

    ・Below is customer measured "DAC input revel" - "RF input level".

     It looked like these level is flat and guess the non-linearity is any affect from DAC output side. 

      (Vertical axis is DAC input - RF input: dB, horizontal axis is input level: dBm)

    Please let me know if there any advice or need additional information.

    Best regards,

    Satoshi

  • Satoshi-san,

    Regarding your feedback from the customer:

    FPGA single tone was not have,

    Based on what I am seeing, the customer reports that the gain is varying on the DAC side. However, all the data has the overall RF input to the DAC. If there are gain variations in the RF chain, the DAC will be impacted. Please emphasize the importance of sending FPGA single tone, and check the DAC output itself.

    The FPGA single tone should have varying power level, and check the DAC output. The gain of the DAC should stay flat.

    I.e. Pin vs. Pout should be a linear line with slope of 1dB/1dB. 

    i.e. Gain vs. Pin should be flat line with a constant gain.

    I update gain graph for RF to DAC output below. (Vertical axis is gain: dB, horizontal axis is input level: dBm)

    Please advise the difference of four lines. Which line is the expected line? if the vertical axis is gain (dB), we should expect flat line, correct? What are the different settings in these four lines that causes the gain to change? 

    Please double check if the vertical axis is indeed gain, as oppose to Pout.

    What does the customer mean by "DAC gain", please advise. Which adjustment is made within the DAC to have these four lines generated? 

  • Hi Kang

    Thank you for advice.

    I requesting to customer about get FPGA single tone.

    About RF to DC output graph, I apologize less information.

     ・Yellow: +5dB, Gray: 0dB, Orange: -5dB, Blue: -10dB

    ・Vertical axis is gain (dB).

    ・"DAC gain" is setting gain of four above lines.

    ・Yes, customer's expect is flat line, and prove the reason of non-flat line.

    Best regards,

    Satoshi

  • Hi Satoshi-san,

    Please also help with the following:

    "DAC gain" is setting gain of four above lines.

    Please ask the customer to specify the exact register settings used to adjust the DAC gain. This is needed to understand the reason for non-flat line. Thank you.

  • Hi Kang

    I understood, I'll feedback to you if there update the single tone and register setting.

    About your advice below, please let me know about detailed about flat line and any other condition.

    -----------------------------------

    The FPGA single tone should have varying power level, and check the DAC output. The gain of the DAC should stay flat.

    I.e. Pin vs. Pout should be a linear line with slope of 1dB/1dB. 

    i.e. Gain vs. Pin should be flat line with a constant gain.

    -----------------------------------

    Best regards,

    Satoshi

  • Hello Kang,

    I'm an AFAE working with Mr. Satoshi.

    DAC gain is adjusted as follows:

    #1 DAC gain -5dB

    adr:0x0032 -> 0x823F

    #2 DAC gain -10dB

    adr:0x0032 -> 0x8400

    #3 DAC gain +3dB

    adr:0x0032 -> 0x85A6.

    One more thing, could you please elaborate on your comment?

    Based on what I am seeing, the customer reports that the gain is varying on the DAC side. However, all the data has the overall RF input to the DAC. If there are gain variations in the RF chain, the DAC will be impacted.

    Do you mean the RF goes into the DAC input over the air? If so, it sounds like the other RF portion on the board should stop or evaluation should be done on the separate board. What do you think?

    And also, my customer requests to reproduce the DAC gain effect on TI EVM. Could you please support? 

    Regards,

    Itoh 

  • Itoh-san

    DAC gain is adjusted as follows:

    #1 DAC gain -5dB

    adr:0x0032 -> 0x823F

    #2 DAC gain -10dB

    adr:0x0032 -> 0x8400

    #3 DAC gain +3dB

    adr:0x0032 -> 0x85A6.

    Thank you. This helps.

    One more thing, could you please elaborate on your comment?

    Based on what I am seeing, the customer reports that the gain is varying on the DAC side. However, all the data has the overall RF input to the DAC. If there are gain variations in the RF chain, the DAC will be impacted.

    Do you mean the RF goes into the DAC input over the air? If so, it sounds like the other RF portion on the board should stop or evaluation should be done on the separate board. What do you think?

    I mean the customer should send only patterns from FPGA to DAC. Not include the input amplifier + ADC. Please evaluate only the FPGA + DAC to avoid additional variables

    And also, my customer requests to reproduce the DAC gain effect on TI EVM. Could you please support? 

    will show example measurements.

  • Itoh-san,

    one test that I will do is to utilize the DAC's input constant value (to replace JESD204 data) with ranges from -32k to 32k. With the DAC's NCO enabled, the customer will observe a CW tone. To do so, do the following:

    1. set the DAC gain to -5dB, as a starting point

    2. enable SPIDAC ENABLE with register 0x2F = 0x01 (depending on the DAC slice)

    3. program SPIDAC in register 0x30. Full-scale = 0x3FFF (note, -3dBFS). Since both I and Q are now DC with 0x3FFF, the CW NCO mixer will be at 0dBFS output. (note: sinwT + coswT = sqrt(2)*sin(WT + 45degree). You will see full-scale output at the output of the NCO 

    4. note the output power. You should see 3dBm at the DAC output (with loss of cable compensated)

    5. back off the SPIDAC in register 0x30 by 1dB (i.e. 0x3909). You should now observe 2dBm at DAC output

    6. plot Pin (SPIDAC) vs. Pout. in steps

    7. repeat again for DACGAIN = 3dB. You will note that the maximum input of SPIDAC should be 0x2d4e due to the additional gain in the signal chain. You cannot exceed the value

  • Hi Kang-san,

    OK, I'll ask my customer to do additional test as you suggested.

    I shared you the FPGA single tone result offline, so please check.

     The results didn't change, so could you please tell me the background why you requested single tone?

    Also, I and customer will appreciate your EVM measurement for reference.

    Regards,

    Itoh

  • Itoh-san,

    Yes, will try to check on EVM by the end of this week to give you some preliminary results. 

  • Itoh-san

    As expected, the DAC gain is a digital process and will not impact the analog gain linearity. The DAC gain is a simple mathematic realized in the digital domain of the DAC. You may see in the EVM measurements that the DAC gain does not change the Pin/Pout relationship. 

    Please ask the customer to download our HSDC PRO software and generate the tone files to upload to their FPGA to double check tone generation accuracy. Thank you. 

  • Hi Kang-san,

    Thank you so much for your kind measurement! Now I'm more confident that DAC38RF80 shouldn't be the cause.

    Could you please let me know the tone frequency you checked? Did you check it with 3.5GHz single tone?

    The customer checked SPIDAC test results also have the non linearity, so they are currently checking the output circuit and measurement set up.

    I'll update later.

    Regards,

    Itoh 

  • Hi Itoh-san,

    I did not check with 3.5GHz. Is this what the customer is using?

    I have only tested with 30MHz, per the EVM user's guide setup.

    Please keep in mind the gain setting is entirely a digital implementation. It should not impact DAC output (analog) gain. For instance, the gain setting at +3dB should also have the same analog behavior at -3dB. 

    -Kang

  • Hi Kang-san,

    Yes, the customer is using 3.5GHz. If the frequency could affect the Pin/Pout relationship, could you please double check it on the EVM?

    Also, I don't find the 30MHz single tone is used from the EVM user guide. Could you please elaborate on that? 

    Regards,

    Itoh

  • Hi Itoh-san,

    Please find below (attached link) for measurement done on the DAC38RF8x EVM at 3.5GHz output. You will find for different gain settings, the Pin vs. Pout relationship remains the same (with different in  output power due to the digital gain setting)

    The digital gain setting is implemented digitally as multiplication factor. Therefore, it will have no impact to the analog output Pout and distortions (unless you digitally saturate the DUC chain).

    Thank you. 

  • Hi Itoh-san,

    2nd tab of the measurements contains 30MHz data, in comparison to the first tab where it is measured at 3.5GHz. 

  • Hi Kang-san,

    Thank you for your measurement!

    I plotted your Pout - Pin from your measurement.

    As my customer mentions, when input tone is small, Pout - Pin gets smaller.

    Also this tendency goes intense when the gain is lower.

    Therefore, my customer is seeing the deteriorated waveform in their system when the input tone is small.

    Could you please comment?

    Regards,

    Itoh  

  • Itoh-san,

    Ok, I see. This tendency will show up at higher gain as well. It is just that the gain variation will occur at even smaller input signal (due to the additional digital gain) for the larger gain

    I have plotted two plots. I have extended the input range for the measurement further for the 3dB gain when compared to the -5dB gain. You can see the gain variation is simply extended 8dB later for the 3dB gain case. This is measured at 3500MHz.

    I have also measured again at 30MHz. You can see the input range for the gain variation for both 3dB and -5dB gain case are even further extended.

    For instance, at -5dB gain, for 3500MHz, the gain variation occurs at input = -40dBFS. For 30MHz, the gain variation occurs at input = -50dBFS.

    There is a reason for this: the DAC output current at lower bits (i.e. lower input scales) may have finite slew rate when charging and discharging the output RF circuits and parasitic due to PCBs and R/L/C components. For instance, at -40dBFS, the 7th bits is the primary switching matrix for the DAC output. With 40mA full-scale, the output current is approximately 40mA/2^7 = 300uA. These types of current will have longer settling time, especially at 3500MHz due to parasitic capacitance.

    The settling time for the DAC is finite. For the 30MHz output frequency, the DAC output can settle completely for each sine wave. However, for 3500MHz output frequency, the DAC output may not settle completely before the next transition.

    The customer may try to reduce the DAC output load further and reduce the parasitic capacitance to see if the situation can help. We can discuss further.